Datasheet

FlexCAN
25-14 Freescale Semiconductor
The FlexCAN responds to any bus state as described in the protocol, e.g. transmit error active or error
passive flag, delay its transmission start time (Error Passive) and avoid any influence on the bus when in
Bus Off state. The following are the basic rules for FlexCAN bus state transitions:
• If the value of TXCTR or RXCTR increases to be greater than or equal to 128, the FCS field in the
error status register is updated to reflect it (set Error Passive state).
• If the FlexCAN state is Error Passive, and either TXCTR counter or RXCTR then decrements to a
value less than or equal to 127 while the other already satisfies this condition, the ESTAT[FCS]
field is updated to reflect it (set Error Active state).
• If the value of the TXCTR increases to be greater than 255, the ESTAT[FCS] field is updated to
reflect it (set Bus Off state) and an interrupt may be issued. The value of TXCTR is then reset to
zero.
• If the FlexCAN state is Bus_Off, then TXCTR, together with an internal counter are cascaded to
count the 128 occurrences of 11 consecutive recessive bits on the bus. Hence, TXCTR is reset to
zero, and counts in a manner where the internal counter counts 11 such bits and then wraps around
while incrementing the TXCTR. When TXCTR reaches the value of 128, ESTAT[FCS] is updated
to be Error Active, and both error counters are reset to zero. At any instance of dominant bit
following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to
zero, but does NOT affect the TXCTR value.
• If during system start-up, only one node is operating, then its TXCTR increases with each message
it’s trying to transmit as a result of ACK_ERROR. A transition to bus state Error Passive should
be executed as described, while this device never enters the Bus_Off state.
• If the RXCTR increases to a value greater than 127, it is no longer incremented, even if more errors
are detected while being a receiver. At the next successful message reception, the counter is set to
a value between 119 and 127, in order to return to Error Active state.
25.4.10 FlexCAN Initialization Sequence
Initialization of the FlexCAN includes the initial configuration of the message buffers and configuration
of the CAN communication parameters following a reset, as well as any reconfiguration which may be
required during operation. The following is a generic initialization sequence for the FlexCAN:
1. Initialize all operation modes
a) Initialize the transmit and receive pin modes in control register 0 (CANCTRL0).
b) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW
in control registers 1 and 2 (CANCTRL[1:2]).
c) Select the S-clock rate by programming the PRESDIV register.
d) Select the internal arbitration mode (LBUF bit in CANCTRL1).
2. Initialize message buffers
a) The control/status word of all message buffers must be written either as an active or inactive
message buffer.
b) All other entries in each message buffer should be initialized as required.
3. Initialize mask registers for acceptance mask as needed
4. Initialize FlexCAN interrupt handler
a) Initialize the interrupt configuration register (ICRn) with a specific request level and vector
base address.
b) Set the required mask bits in the IMASK register (for all message buffer interrupts), in
CANCTRL0 (for bus off and error interrupts), and in CANMCR for the WAKE interrupt.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3