Datasheet

DMA Timers (DTIM0–DTIM3)
21-2 Freescale Semiconductor
Figure 21-1 is a block diagram of one of the four identical timer modules.
Figure 21-1. DMA Timer Block Diagram
21.1.2 Features
Each DMA timer module has:
• Maximum timeout period of 219,902 seconds at 80 MHz (~61 hours)
• 12.5-ns resolution at 80 MHz
• Programmable sources for the clock input, including external clock
• Programmable prescaler
• Input-capture capability with programmable trigger edge on input pin
• Programmable mode for the output pin on reference compare
• Free run and restart modes
• Programmable interrupt or DMA request on input capture or reference-compare
DMA Timer
Divider
DMA Timer Mode Register (DTMRn)
Prescaler Mode Bits
DMA Timer Counter Register (DTCNn)
31 0
DMA Timer Reference Register (DTRRn)
31 0
DMA Timer Capture Register (DTCRn)
31 0
DMA Timer Event Register (DTERn)
Capture
Detection
clock
(contains incrementing value)
(reference value for comparison with DTCN)
(indicates capture or when DTCN = DTRRn)
Interrupt Request
Clock
Generator
DMA Timer Extended Mode
Register (DTXMRn)
DMA Request
0
0
15
7
7
0
Internal Bus Clock
(÷1 or ÷16
)
DMA Timer
Internal Bus to/from DMA Timer Registers
(latches DTCN value when triggered byDTINn)
DTOUTn
DTINn
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3