Datasheet

Fast Ethernet Controller (FEC)
Freescale Semiconductor 17-43
17.5.15.1 Transmission Errors
17.5.15.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining
buffers for that frame are then flushed and closed, and EIR[UN] is set. The FEC then continues to the next
transmit buffer descriptor and begin transmitting the next frame. The UN interrupt is asserted if enabled
in the EIMR register.
17.5.15.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed
and closed, and EIR[RL] is set. The FEC then continues to the next transmit buffer descriptor and begins
transmitting the next frame. The RL interrupt is asserted if enabled in the EIMR register.
17.5.15.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining buffers for that frame are flushed and closed, and EIR[LC] is set. The FEC
then continues to the next transmit buffer descriptor and begin transmitting the next frame. The LC
interrupt is asserted if enabled in the EIMR register.
17.5.15.1.4 Heartbeat
Some transceivers have a self-test feature called heartbeat or signal quality error. To signify a good
self-test, the transceiver indicates a collision to the FEC within four microseconds after completion of a
frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision
error on the network, but is rather an indication that the transceiver continues to function properly. This is
the heartbeat condition.
If TCR[HBC] is set and the heartbeat condition is not detected by the FEC after a frame transmission, a
heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets EIR[HB], and generates the
HBERR interrupt if it is enabled.
17.5.15.2 Reception Errors
17.5.15.2.1 Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, FEC sets RxBD[OV].
All subsequent data in the frame is discarded and subsequent frames may also be discarded until the
receive FIFO is serviced by the DMA and space is made available. At this point the receive frame/status
word is written into the FIFO with the OV bit set. The driver must discard this frame.
17.5.15.2.2 Non-Octet Error (Dribbling Bits)
The Ethernet controller manages up to seven dribbling bits when the receive frame terminates past an
non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, the
frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, no error is reported.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3