Datasheet

Fast Ethernet Controller (FEC)
17-32 Freescale Semiconductor
17.5.4 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, hardware is ready for operation.
Table 17-34 shows microcontroller initialization operations.
17.5.5 User Initialization (After Setting ECR[ETHER_EN])
After setting ECR[ETHER_EN], you can set up the buffer/frame descriptors and write to TDAR and
RDAR. Refer to Section 17.5.1, “Buffer Descriptors,” for more details.
17.5.6 Network Interface Options
The FEC supports an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps
Ethernet. The RCR[MII_MODE] bit select the interface mode. In MII mode (RCR[MII_MODE] set),
there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC. Table 17-35 shows
these signals.
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
Table 17-34. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
Table 17-35. MII Mode
Signal Description EMAC pin
Transmit Clock FEC_TXCLK
Transmit Enable FEC_TXEN
Transmit Data FEC_TXD[3:0]
Transmit Error FEC_TXER
Table 17-33. FEC User Initialization (Before ECR[ETHER_EN]) (continued)
Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3