Datasheet

Fast Ethernet Controller (FEC)
Freescale Semiconductor 17-23
17.4.21 FIFO Receive Start Register (FRSR)
FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary between the transmit
and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes
before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR
inclusive.
Hardware initializes the FRSR register at reset. FRSR only needs to be written to change the default value.
17.4.22 Receive Descriptor Ring Start Register (ERDSR)
ERDSR points to the start of the circular receive buffer descriptor queue in external memory. This pointer
must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized prior to operation.
Table 17-24. FRBR Field Descriptions
Field Description
31–10 Reserved, read as 0 (except bit 10, which is read as 1).
9–2
R_BOUND
Read-only. Highest valid FIFO RAM address.
1–0 Reserved, read as 0.
IPSBAR
Offset:
0x1150 Access: User read/write
31302928272625242322212019181716151413121110987654321 0
R00000000000000 0 0000001
R_FSTART
00
W
Reset0000000000000000000001010000000 0
Figure 17-21. FIFO Receive Start Register (FRSR)
Table 17-25. FRSR Field Descriptions
Field Description
31–11 Reserved, must be cleared.
10 Reserved, must be set.
9–2
R_FSTART
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper
operation, ensure that R_FSTART is set to 0x48 or greater.
1–0 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3