Datasheet

Synchronous DRAM Controller Module
Freescale Semiconductor 15-21
Figure 15-12. SDRAM Configuration
The DACRs should be programmed as shown in Figure 15-13.
This configuration results in a value of DACR0 = 0xFF88_0300, as described in Table 15-28. DACR1
initialization is not needed because there is only one block. Subsequently, DACR1[RE,IMRS,IP] should
be cleared; everything else is a don’t care.
31 18 17 16
Field BA —
Setting 1111_1111_1000_10xx
(hex) F F 8 8
151413121110 876543210
Field RE — CASL — CBM — IMRS PS IP —
Setting 0000_x011_x000_0000
(hex) 0300
Figure 15-13. DACR Register Configuration
Table 15-28. DACR Initialization Values
Bits Name Setting Description
31–18 BA 1111_1111_
1000_10
Base address. So DACR0[31–16] = 0xFF88, placing the starting
address of the SDRAM accessible memory at 0xFF88_0000.
17–16 — Reserved. Don’t care.
15 RE 0 Keeps auto-refresh disabled because registers are being set up
at this time.
14 — Reserved. Don’t care.
13–12 CASL 00 Indicates a delay of data 1 cycle after S
CAS is asserted
11 — Reserved. Don’t care.
10–8 CBM 011 Command bit is pin 20 and bank selects are 21 and up.
7 — Reserved. Don’t care.
6 IMRS 0 Indicates MRS command has not been initiated.
5–4 PS 00 32-bit port.
Bank 0
1 Mbyte
512 Kbyte
512 Kbyte
SDRAM Component
Accessible
Memory
Bank 1
1 Mbyte
512 Kbyte
512 Kbyte
Bank 2
1 Mbyte
512 Kbyte
512 Kbyte
Bank 3
1 Mbyte
512 Kbyte
512 Kbyte
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3