Datasheet

Synchronous DRAM Controller Module
15-20 Freescale Semiconductor
15.3.1 SDRAM Interface Configuration
To interface this component to the DRAM controller, use the connection table that corresponds to a 32-bit
port size with 8 columns (Table 15-24). Two pins select one of four banks when the part is functional.
Table 15-26 shows the proper hardware connections.
15.3.2 DCR Initialization
At power-up, the DCR has the following configuration if synchronous operation and SDRAM address
multiplexing are desired.
This configuration results in a value of 0x0026 for DCR, as shown in Table 15-27.
15.3.3 DACR Initialization
As shown in Figure 15-12, the SDRAM is programmed to access only the second 512-Kbyte block of each
1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF88_0000.
Continuous page mode feature is used.
Table 15-26. SDRAM Hardware Connections
Processor Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22
SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1
15 14 13 12 11 10 9 8 0
Field — — NAM COC IS RTIM RC
Setting 0000_0000_0010_0110
(hex) 0026
Figure 15-11. Initialization Values for DCR
Table 15-27. DCR Initialization Values
Bits Name Setting Description
15 — 0 Reserved.
14 — 0 Reserved.
13 NAM 0 Indicating SDRAM controller multiplexes address lines internally
12 COC 0 SCKE is used as clock enable instead of command bit because user is not multiplexing
address lines externally and requires external command feed.
11 IS 0 At power-up, allowing power self-refresh state is not appropriate because registers are being
set up.
10–9 RTIM 00 Because t
RC
value is 70 ns, indicating a 3-clock refresh-to-ACTV timing.
8–0 RC 0x26 Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625
µs for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by 1 and
multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3