Datasheet

Synchronous DRAM Controller Module
15-4 Freescale Semiconductor
15.2.1 DRAM Controller Signals
Table 15-2 describes the behavior of DRAM signals in synchronous mode.
15.2.2 Memory Map for SDRAMC Registers
The DRAM controller registers memory map is shown in Table 15-3.
15.2.2.1 DRAM Control Register (DCR)
The DCR, shown in Figure 15-2, controls refresh logic.
Table 15-2. Synchronous DRAM Signal Connections
Signal Description
SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by
the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS.
SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by
the SDRAM. SCAS
should be connected to the corresponding SDRAM SCAS.
DRAMW DRAM read/write. Asserted for write operations and negated for read operations.
SDRAM_CS[1:0
]
Row address strobe. Select each memory block of SDRAMs connected to the processor. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SCKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs.
Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down
mode in which operations are suspended or capable of entering self-refresh mode. SCKE functionality is
controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide
command-bit functionality.
BS[3:0] Column address strobe. BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals
(or mask qualifiers) of the SDRAMs.
Table 15-3. DRAM Controller Registers
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x040 DRAM control register (DCR) [p. 15-4] —
0x044 —
0x048 DRAM address and control register 0 (DACR0) [p. 15-6]
0x04C DRAM mask register block 0 (DMR0) [p. 15-8]
0x050 DRAM address and control register 1 (DACR1) [p. 15-6]
0x054 DRAM mask register block 1 (DMR1) [p. 15-8]
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3