Datasheet

Freescale Semiconductor 13-1
Chapter 13
External Interface Module (EIM)
This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 15,
“Synchronous DRAM Controller Module,” describes DRAM cycles.
NOTE
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used
for the bus.
13.1 Features
The following list summarizes bus operation features:
• Up to 24 bits of address and 32 bits of data
• Access 8-, 16-, and 32-bit data port sizes
• Generates byte, word, longword, and line-size transfers
• Burst and burst-inhibited transfer support
• Optional internal termination for external bus cycles
13.2 Bus and Control Signals
Table 13-1 summarizes the bus signals described in Chapter 14, “Signal Descriptions”.
Table 13-1. ColdFire Bus Signal Summary
Signal Name Description I/O CLKOUT Edge
A[23:0] Address bus O Rising
BS
1
1
These signals change after the falling edge. In the Electrical Specifications, these signals are
specified off of the rising edge because CLKIN is squared up internally.
Byte selects O Falling
CS
[6:0]
1
Chip selects O Falling
D[31:0] Data bus I/O Rising
OE
1
Output enable O Falling
R/W Read/write O Rising
SIZ[1:0] Transfer size O Rising
TA
Transfer acknowledge I Rising
TIP Transfer in progress O Rising
TS
Transfer start O Rising
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3