Datasheet

Chip Select Module
12-8 Freescale Semiconductor
Figure 12-4. Chip Select Control Registers (CSCRn)
Table 12-8 describes CSCRn fields.
15 14 13 10 9 8 7 6 5 4 3 2 0
Field — WS — AA PS1 PS0 BEM BSTR BSTW —
Reset: CSCR0 — 11_11 — 1 D19 D18 — —
Reset: Other CSCRs Uninitialized
R/W R/W
Address 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6)
Table 12-8. CSCRn Field Descriptions
Bits Name Description
15–14 — Reserved, should be cleared.
13–10 WS Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA
must be asserted by
the external system regardless of the number of wait states generated. In that case, the external
transfer acknowledge ends the cycle. An external TA supercedes the generation of an internal TA.
9 — Reserved, should be cleared.
8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses
specified by the chip select address.
0 No internal TA
is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the
external system asserts an external TA
before the wait-state countdown asserts the internal TA, the
cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6 PS Port size. Specifies the width of the data associated with each chip select. It determines where data is
driven during write cycles and where data is sampled during read cycles. See Section 12.3.1.1, “8-,
16-, and 32-Bit Port Sizing”.
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must
be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the
appropriate mode of byte enable in support of these SRAMs.
0BS
is not asserted for read. BS is asserted for data write only.
1BS is asserted for read and write accesses.
4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and
16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3