Datasheet

Clock Module
9-10 Freescale Semiconductor
9.7 Functional Description
This subsection provides a functional description of the clock module.
9.7.1 System Clock Modes
The system clock source is determined during reset (see Table 27-8). The values of CLKMOD[1:0] are
latched during reset and are of no importance after reset is negated. If CLKMOD1 or CLKMOD0 is
changed during a reset other than power-on reset, the internal clocks may glitch as the system clock source
is changed between external clock mode and PLL clock mode. Whenever CLKMOD1 or CLKMOD0 is
changed in reset, an immediate loss-of-lock condition occurs.
Table 9-7 shows the clockout frequency to clockin frequency relationships for the possible system clock
modes.
2 LOCS Sticky indication of whether a loss-of-clock condition has occurred at any time since
exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks
are operating normally. LOCS = 1 when system clocks have failed due to a reference
failure or PLL failure.
After entering stop mode with FWKUP set and the PLL and oscillator intentionally
disabled (STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator
starts up. During this time, LOCS is temporarily set regardless of LOCEN. It is cleared
once the oscillator comes up and the PLL is attempting to lock.
If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag
does not reflect the current loss-of-clock condition.
A loss-of-clock condition can be detected only if LOCEN = 1 or the oscillator has not
yet returned from exit from stop mode with FWKUP = 1.
1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit
from stop mode with FWKUP = 1
0 Loss-of-clock not detected since exiting reset
Note: The LOCS flag is always 0 in external clock mode.
1–0 — Reserved, should be cleared.
Table 9-6. System Clock Modes
PLLMODE:PLLSEL:PLLREF Clock Mode
000 External clock mode
100 1:1 PLL mode
110 Normal PLL mode with external clock reference
111 Normal PLL mode with crystal reference
Table 9-7. Clock Out and Clock In Relationships
System Clock Mode PLL Options
1
Normal PLL clock mode f
sys
= f
ref
× 2(MFD + 2)/2
RFD
1:1 PLL clock mode f
sys
= f
ref
External clock mode f
sys
= f
ref
Table 9-5. SYNSR Field Descriptions (continued)
Bit(s) Name Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3