Datasheet

ColdFire Flash Module (CFM)
Freescale Semiconductor 6-17
initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug modes
and when the MCU boots in master mode or emulation mode.
6.4.1 Read Operations
A valid read operation occurs whenever a transfer request is initiated by the ColdFire core, the address is
equal to an address within the valid range of the CFM memory space, and the read/write control indicates
a read cycle.
In order to reduce power at low system clock frequencies, the sense amplifier timeout (SATO) block
minimizes the time during which the sense amplifiers are enabled for read operations. The sense amplifier
enable signals to the Flash timeout after approximately 50 ns.
6.4.2 Write Operations
A valid write operation occurs whenever a transfer request is initiated by the ColdFire core, the address is
equal to an address within the valid range of the CFM memory space, and the read/write control indicates
a write cycle.
The action taken on a valid CFM array write depends on the subsequent user command issued as part of a
valid command sequence. Only aligned 32-bit write operations are allowed to the CFM array. Byte and
word write operations will result in a cycle termination transfer error.
6.4.3 Program and Erase Operations
Read and write operations are both used for the program and erase algorithms described in this subsection.
These algorithms are controlled by a state machine whose timebase is derived from the CFM module clock
via a programmable counter.
The command register and associated address and data buffers operate as a two stage FIFO so that a new
command along with the necessary address and data can be stored while the previous command is still in
progress. This pipelining speeds when programming more than one longword on a specific row, as the
charge pumps can be kept on in between two programming commands, thus saving the overhead needed
to set up the charge pumps. Buffer empty and command completion are indicated by flags in the CFM user
status register. Interrupts will be requested if enabled.
6.4.3.1 Setting the CFMCLKD Register
Prior to issuing any program or erase commands, CFMCLKD must be written to set the Flash state
machine clock (FCLK). The CFM module runs at the system clock frequency ÷ 2, but FCLK must be
divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the following
procedure to set the PRDIV8 and DIV[5:0] bits in CFMCLKD:
1. If f
SYS
÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.
2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result
and discard any fraction. Do not round the result.
3. Thus the Flash state machine clock will be:
f
SYS
2 x 200kHz x (1 + (PRDIV8 x 7))
DIV[5:0] =
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3