Datasheet

ColdFire Flash Module (CFM)
Freescale Semiconductor 6-9
6.3.4.2 CFM Clock Divider Register (CFMCLKD)
The CFMCLKD is used to set the frequency of the clock used for timed events in program and erase
algorithms.
All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once.
7 CBEIE Command buffer empty interrupt enable. The CBEIE bit is readable and writable.
CBEIE enables an interrupt request when the command buffer for the Flash
physical blocks is empty.
1 Request an interrupt whenever the CBEIF flag is set.
0 Command buffer empty interrupts disabled
6 CCIE Command complete interrupt enable. The CCIE bit is readable and writable.
CCIE enables an interrupt when the command executing for the Flash is
complete.
1 Request an interrupt whenever the CCIF flag is set.
0 Command complete interrupts disabled
5 KEYACC Enable security key writing. The KEYACC bit is readable and only writable if the
KEYEN bit in the CFMSEC register is set.
1 Writes to the Flash array are interpreted as keys to open the back door.
0 Writes to the Flash array are interpreted as the start of a program, erase, or
verify sequence.
4–0 — Reserved, should be cleared.
765 0
Field DIVLD PRDIV8 DIV
Reset 0000_0000
R/W R R/W
Address IPSBAR + 0x1D_0002
Figure 6-5. CFM Clock Divider Register (CFMCLKD)
Table 6-5. CFMCLKD Field Descriptions
Bits Name Description
7 DIVLD Clock divider loaded
1 CFMCLKD has been written since the last reset.
0 CFMCLKD has not been written.
6 PRDIV8 Enable prescaler divide by 8
1 Enables a prescaler that divides the CFM clock by 8 before it enters the
CFMCLKD divider.
0 The CFM clock is fed directly into the CFMCLKD divider.
5–0 DIV Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the
CFM input clock down to a frequency between 150 kHz and 200 kHz. The
frequency range of the CFM clock is 150 kHz to 102.4 MHz.
Table 6-4. CFMCR Field Descriptions
Bits Name Description
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3