Datasheet

Cache
Freescale Semiconductor 4-3
of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
4.2.1 Cache Control Register (CACR)
The CACR controls the operation of the cache. The CACR provides a set of default memory access
attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit, write-only supervisor control register. It is accessed in the CPU address space via
the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug
mode (BDM). Therefore, the register diagram, Figure 4-2, is shown as read/write. At system reset, the
entire register is cleared.
Table 4-1. Cache Memory Map
BDM
1
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For
more information see Chapter 30, “Debug Support.”
Register
Width
(bits)
Access
2
2
Readable through debug.
Reset Value Section/Page
0x002 Cache Control Register (CACR) 32 W 0x0000_0000 4.2.1/4-3
0x004 Access Control Register 0 (ACR0) 32 W See Section 4.2.2/4-6
0x005 Access Control Register 1 (ACR1) 32 W See Section 4.2.2/4-6
BDM: 0x002 (CACR) Access: Supervisor write-only
Debug read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CENB
0 0
CPD CFRZ
00
CINV DISI DISD INVI INVD
0 000
W
Reset0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0000
CEIB DCM DBWE
0 0
DWP EUSP
0 0
CLNF
W
Reset0000000000000000
Figure 4-2. Cache Control Register (CACR)
Table 4-2. CACR Field Descriptions
Field Description
31
CENB
Cache enable.
The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI
(disable instruction caching) and DISD (disable data caching) bits, control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 4-3 describes cache configuration.
30–29 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3