MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual Devices Supported: MCF5214 MCF5216 MCF5280 MCF5281 MCF5282 Document Number: MCF5282UM Rev.
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.
Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules DMA Timers Queued Serial
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B IND Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Pro
Chapter 1 Overview 1.1 1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 2.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.10 Memory Base Address Registers (RAMBAR, FLASHBAR) . . . . . . . . . . . . . . . 2-8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.2 Instruction Set Architecture (ISA_A+) . . . . . . .
3.3.2 3.3.3 3.3.4 3.3.5 3.3.1.2 Saving and Restoring the EMAC Programming Model . . . . . . . . . . . . 3.3.1.3 MULS/MULU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1.4 Scale Factor in MAC or MSAC Instructions . . . . . . . . . . . . . . . . . . . . EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 6.5 6.6 6.7 6.3.4.3 CFM Security Register (CFMSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.4 CFM Protection Register (CFMPROT) . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.5 CFM Supervisor Access Register (CFMSACC) . . . . . . . . . . . . . . . . . 6.3.4.6 CFM Data Access Register (CFMDACC) . . . . . . . . . . . . . . . . . . . . . . 6.3.4.7 CFM User Status Register (CFMUSTAT) . . . . . . . . . . . . . . . . . . . . . . 6.3.4.8 CFM Command Register (CFMCMD) . . . . . . .
7.3.2.7 DMA Controller (DMAC0–DMA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.8 UART Modules (UART0, UART1, and UART2) . . . . . . . . . . . . . . . . . . 7-8 7.3.2.9 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.10 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.11 DMA Timers (DMAT0–DMAT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.
8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Chapter 9 Clock Module 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1 Normal PLL Mode . . . . . . . . . . . .
10.2 10.3 10.4 10.5 10.1.1.1 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.1.1.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.1.3 Interrupt Vector Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Register Descriptions . . . . . . . . .
Chapter 13 External Interface Module (EIM) 13.1 13.2 13.3 13.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Bus and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . .
14.2.3.2 Reset Out (RSTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.3 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.4 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.5 Clock Output (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 Chip Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.2.12.1 DMA Timer 0 Input (DTIN0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.2 DMA Timer 0 Output (DTOUT0) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.3 DMA Timer 1 Input (DTIN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.4 DMA Timer 1 Output (DTOUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.5 DMA Timer 2 Input (DTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.6 DMA Timer 2 Output (DTOUT2) . . . . . .
.2.1 DRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 Memory Map for SDRAMC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.1 DRAM Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1) . . . . . . . . 15-6 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1) . . . . . . . . . . . . . . 15-8 15.2.
Chapter 17 Fast Ethernet Controller (FEC) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.5.2.1 Hardware Controlled Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.3 User Initialization (Prior to Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . 17.5.4 Microcontroller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.5 User Initialization (After Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . . . 17.5.6 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.
19.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 Chapter 20 General Purpose Timer Modules (GPTA and GPTB) 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Features . . . . . . . . . . . . . . . . . . . . . . . .
20.8.3 Pulse Accumulator Input (PAIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.8.4 Timer Overflow (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 Chapter 21 DMA Timers (DTIM0–DTIM3) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.1.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.3 Transfer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.4 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.5 Data Transfer . . . . . . . . . . . . . . . . . . . . . . .
23.5.1.1 Setting up the UART to Generate Core Interrupts . . . . . . . . . . . . . 23-26 23.5.1.2 Setting up the UART to Request DMA Service . . . . . . . . . . . . . . . 23-27 23.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29 Chapter 24 I C Interface 2 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . .
25.3.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3.2 Message Buffer Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.4 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.4.1 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.4.2 Receive Process . . . . . . . . . . . . . .
26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.
27.6.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.5 Clock Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.6 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7 Reset . . . . . . . . . . . . . . . . .
28.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.1 Result Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2.1 External Multiplexing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2.2 Module Version Options . . . . . . . . . . . . . . . .
28.9.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10.1Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10.2Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.5 30.6 30.7 30.8 30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR) . . . . . . . . . . . . 30.4.7 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.2 BDM Serial Interface . . . . . . . . . . . . . . . . . . . .
31.5.3.1 External Test Instruction (EXTEST) . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.3 SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.4 TEST_LEAKAGE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.5 ENABLE_TEST_CTRL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.6 HIGHZ Instruction . . . . . . .
Appendix A Register Memory Map Appendix B Revision History B.1 B.2 B.3 B.4 B.5 B.6 B.7 Changes Between Rev. 0 and Rev. 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Changes Between Rev. 0.1 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Changes Between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Changes Between Rev. 2 and Rev. 2.1 . . . . . . . . . . . . . . . . . . . . . . . . .
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
About This Book The primary objective of this user’s manual is to define the functionality of the MCF5282 processor for use by software and hardware developers. The information in this book, except for changes to the flash and Ethernet functionality, also applies to the MCF5280, MCF5281, MCF5216, and MCF5214. The information in this book is subject to change without notice, as described in the disclaimers on the title page.
• • • • User’s manuals — These books provide details about individual ColdFire implementations and are intended to be used in conjunction with the ColdFire Programmers Reference Manual. Data sheets — Data sheets provide specific data regarding pin-out diagrams, bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. Product briefs — Each device has a product brief that provides an overview of its features.
Chapter 1 Overview This chapter provides an overview of the microprocessor features, including the major functional components. 1.1 Key Features A block diagram of the MCF528x and MCF521x is shown in Figure 1-1.
Overview • • • — Memory-based flexible descriptor rings — Media-independent interface (MII) to transceiver (PHY) FlexCAN 2.0B Module — Includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.
Overview • • • • Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable master bit rates — Up to 16 pre-programmed transfers Queued analog-to-digital converter (QADC) — 8 direct, or up to 18 multiplexed, analog input channels — 10-bit resolution +/- 2 counts accuracy — Minimum 7 μS conversion time — Internal sample and hold — Programmable input sample time for various source impedances — T
Overview • • • • • • — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel per timer Four periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down Software watchdog timer — 16-bit counter — Low-power mode support Phase locked loop (PLL) — Crystal or external oscillator reference — 2- to 10-MHz reference frequency for normal PLL mode — 33- to 80-MHz (66 MHz for MCF5214/16) oscillator reference frequency fo
Overview • • • • — Ability to boot from internal Flash memory or external memories that are 8, 16, or 32 bits wide Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD) — Status flag indication of source of last reset Chip integration module (CIM) — System configuration during reset — Support for single chip, master, and test modes — Selects one of four clock modes —
Chip Configuration Reset Controller Power Management Overview JTAG Port External Interface Module Test Controller Debug Module Ports Module ColdFire V2 Core Flash Module 64K SRAM Note: Not present on MCF5280 DIV Interrupt Controller 1 Internal Bus Arbiter System Control Module (SCM) Interrupt Controller 0 DMA Controller 2-Kbyte D-Cache/I-Cache Chip Selects Edgeport EMAC DRAM Controller UART0 Serial I/O Clock Module (PLL) UART1 Serial I/O UART2 Serial I/O DMA Timer Modules (DTIM0– D
Overview 1.1.1 Version 2 ColdFire Core The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages.
Overview The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FEC. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an example, system performance can be increased significantly if Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing. 1.1.1.
Overview base address register (RAMBAR), and system control registers that include low-power and core watchdog timer control. 1.1.3 External Interface Module (EIM) The external interface module handles the transfer of information between the internal core and memory, peripherals, or other processing elements in the external address space.
Overview 1.1.8 SDRAM Controller The SDRAM controller provides all required signals for glueless interfacing to a variety of JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SRAS, SCAS, DRAMW, SDRAM_CS[1:0], and SCKE are dedicated SDRAM signals. 1.1.
Overview • • Detection of breaks originating in the middle of a character Start/end break interrupt/status 1.1.11 DMA Timers (DTIM0-DTIM3) There are four independent, DMA-transfer-generating 32-bit timers (DTIM0, DTIM1, DTIM2, DTIM3) on the MCF5282. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals.
Overview byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software, explicitly setting a DCRn[START] bit or the occurrence of a hardware event from one of the on-chip peripheral devices, such as a capture event or an output reference event in a DMA timer (DTIMn) for each channel. The DMA controller supports dual-address mode to on-chip devices. 1.1.
Overview 1.2.4 Queued Serial Peripheral Interface (QSPI) The queued serial peripheral interface module provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU intervention between transfers. 1.2.5 Queued Analog-to-Digital Converter (QADC) The QADC is a 10-bit, unipolar, successive approximation converter. A maximum of 8 analog input channels can be supported using internal multiplexing.
Overview MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 2 ColdFire Core 2.1 Introduction This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual. 2.1.1 Overview As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.
ColdFire Core instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
ColdFire Core Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC arithmetic operations generally affect the entire 48-bit destination.
ColdFire Core Table 2-1. ColdFire Core Programming Model (continued) BDM1 Width Access (bits) Register 0x80F Program Counter (PC) 32 R/W Written with Section/Page MOVEC Reset Value Contents of location 0x0000_0004 No 2.2.5/2-7 Supervisor Access Only Registers 0x002 Cache Control Register (CACR) 32 R/W 0x0000_0000 Yes 2.2.6/2-7 Access Control Register 0–1 (ACR0–1) 32 R/W See Section Yes 2.2.
ColdFire Core BDM: Load: 0x088 + n; n = 0–6 (An) Store: 0x188 + n; n = 0–6 (An) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 2-3. Address Registers (A0–A6) 2.2.
ColdFire Core BDM: Load: 0x08F (A7) Store: 0x18F (A7) 0x800 (OTHER_A7) Access: A7: User or BDM read/write OTHER_A7: Supervisor or BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 2-4. Stack Pointer Registers (A7 and OTHER_A7) 2.2.4 Condition Code Register (CCR) The CCR is the LSB of the processor status register (SR).
ColdFire Core 2.2.5 Program Counter (PC) The PC contains the currently executing instruction address. During instruction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the PC, as appropriate. The PC is a base address for PC-relative operand addressing. The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
ColdFire Core 2.2.9 Status Register (SR) The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode.
ColdFire Core 2.3 2.3.1 Functional Description Version 2 ColdFire Microarchitecture From the block diagram in Figure 2-1, the non-Harvard architecture of the processor is readily apparent. The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional 32-bit data buses. This structure minimizes the core size without compromising performance to a large degree.
ColdFire Core DSOC AGEX RGF Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
ColdFire Core instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle. See Figure 2-11. Operand Execution Pipeline DSOC RGF AGEX Rx new Rx Ry Opword Core Bus Address Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-11.
ColdFire Core Operand Execution Pipeline DSOC AGEX RGF y Ay Opword Core Bus Address d16 Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-12. V2 OEP Embedded-Load Part 1 Operand Execution Pipeline DSOC AGEX Rx RGF new Rx Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data y Figure 2-13.
ColdFire Core For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time. Operand Execution Pipeline DSOC AGEX Ax RGF Ry x Opword Extension 1 Core Bus Address d16 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-14. V2 OEP Register-to-Memory The pipeline timing diagrams of Figure 2-15 depict the execution templates for these three classes of instructions.
ColdFire Core Core clock Register-to-Register OEP.DSOC OC OEP.AGEX next EX Core Bus Embedded-Load OEP.DSOC DS OEP.AGEX OC AG Core Bus next EX op read Register-to-Memory (Store) OEP.DSOC OEP.AGEX DSOC next AGEX op write Core Bus Figure 2-15. V2 OEP Pipeline Execution Templates 2.3.2 Instruction Set Architecture (ISA_A+) The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code.
ColdFire Core Table 2-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details see the ColdFire Family Programmer’s Reference Manual. Table 2-4. Instruction Enhancements over Revision ISA_A Instruction Description BITREV The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
ColdFire Core 3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure 2-16, the processor uses a simplified fixed-length stack frame for all exceptions.
ColdFire Core Table 2-5. Exception Vector Assignments (continued) 1 Vector Number(s) Vector Offset (Hex) Stacked Program Counter Assignment 32–47 0x080–0x0BC Next Trap # 0-15 instructions 48–63 0x0C0–0x0FC — Reserved 64–255 0x100–0x3FC Next Device-specific interrupts Fault refers to the PC of the instruction that caused the exception. Next refers to the PC of the instruction that follows the instruction that caused the fault.
ColdFire Core Table 2-7.
ColdFire Core execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction. 2.3.4.2 Address Error Exception Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is set) results in an address error exception. Any attempted use of a word-sized index register (Xn.
ColdFire Core Table 2-8.
ColdFire Core 3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step. If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2.
ColdFire Core 2.3.4.11 TRAP Instruction Exception The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode. 2.3.4.12 Unsupported Instruction Exception If execution of a valid instruction is attempted but the required hardware is not present in the processor, an unsupported instruction exception is generated.
ColdFire Core ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM to determine the hardware configuration. Information loaded into D0 defines the processor hardware configuration as shown in Figure 2-18.
ColdFire Core Table 2-9. D0 Hardware Configuration Info Field Description (continued) Field Description 11–8 Reserved. 7–4 ISA ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core. 0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (This is the value used for this device.) Else Reserved 3–0 Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
ColdFire Core Table 2-10. D1 Hardware Configuration Information Field Description (continued) Field Description 27–24 CCSZ Configurable cache size. Indicates the amount of instruction/data cache. The cache configuration options available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register.
ColdFire Core • R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1). This section includes the assumptions concerning the timing values and the execution time details. 2.3.5.1 Timing Assumptions For the timing data presented in this section, these assumptions apply: 1. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution.
ColdFire Core ET with { = (d16,PC)} equals ET with { = (d16,An)} ET with { = (d8,PC,Xi*SF)} equals ET with { = (d8,An,Xi*SF)} The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l. Table 2-12. MOVE Byte and Word Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.
ColdFire Core 2.3.5.3 Standard One Operand Instruction Execution Times Table 2-14. One Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx BITREV Dx 1(0/0) — — — — — — — BYTEREV Dx 1(0/0) — — — — — — — CLR.B 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — CLR.W 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — CLR.
ColdFire Core Table 2-15. Two Operand Instruction Execution Times (continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx ASL.L ,Dx 1(0/0) — — — — — — 1(0/0) ASR.
ColdFire Core 2.3.5.5 Miscellaneous Instruction Execution Times Table 2-16. Miscellaneous Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx CPUSHL (Ax) — 11(0/1) — — — — — — LINK.W Ay,#imm 2(0/1) — — — — — — — MOVE.L Ay,USP 3(0/0) — — — — — — — MOVE.L USP,Ax 3(0/0) — — — — — — — MOVE.W CCR,Dx 1(0/0) — — — — — — — MOVE.W ,CCR 1(0/0) — — — — — — 1(0/0) MOVE.
ColdFire Core 2.3.5.6 EMAC Instruction Execution Times Table 2-17. EMAC Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An, xxx.wl Xn*SF) #xxx MAC.L Ry, Rx, Raccx 1(0/0) — — — — — — — MAC.L Ry, Rx, , Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MAC.W Ry, Rx, Raccx 1(0/0) — — — — — — — MAC.W Ry, Rx, , Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MOVE.L y, Raccx 1(0/0) — — — — — — 1(0/0) MOVE.
ColdFire Core NOTE The execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destination location x shown in this table represent the best-case scenario when the store instruction is executed and there are no load or M{S}AC instructions in the EMAC execution pipeline.
Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC) 3.1 Introduction This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. 3.1.1 Overview The EMAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture. The MAC provides functionality in three related areas: 1.
Enhanced Multiply-Accumulate Unit (EMAC) Operand Y Operand X X Shift 0,1,-1 +/- Accumulator(s) Figure 3-1. Multiply-Accumulate Functionality Diagram 3.1.1.1 Introduction to the MAC The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures.
Enhanced Multiply-Accumulate Unit (EMAC) 3.2 Memory Map/Register Definition The following table and sections explain the MAC registers: Table 3-1. EMAC Memory Map BDM1 1 Register Width (bits) Access Reset Value Section/Page 0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 3.2.1/3-3 0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 3.2.2/3-5 0x806 MAC Accumulator 0 (ACC0) 32 R/W Undefined 3.2.
Enhanced Multiply-Accumulate Unit (EMAC) Table 3-2. MACSR Field Descriptions (continued) Field Description 7 OMC Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set to the appropriate constant (see S/U field description) on any operation that overflows the accumulator. After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or the accumulator is directly loaded.
Enhanced Multiply-Accumulate Unit (EMAC) Table 3-2. MACSR Field Descriptions (continued) Field Description 1 V Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the appropriate PAVn flag in the next-state V evaluation. 0 EV Extension overflow.
Enhanced Multiply-Accumulate Unit (EMAC) The and operator enables the MASK use and causes bit 5 of the extension word to be set.
Enhanced Multiply-Accumulate Unit (EMAC) BDM: 0x806 (ACC0) 0x809 (ACC1) 0x80A (ACC2) 0x80B (ACC3) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 Accumulator W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 3-4. Accumulator Registers (ACC0–3) Table 3-5. ACC0–3 Field Descriptions Field Description 31–0 Accumulator 3.2.4 Store 32-bits of the result of the MAC operation.
Enhanced Multiply-Accumulate Unit (EMAC) BDM: 0x808 (ACCext23) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W ACC2U ACC2L 8 7 ACC3U 6 5 4 3 2 1 0 ACC3L Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 3-6. Accumulator Extension Register (ACCext23) Table 3-7. ACCext23 Field Descriptions Field 3.
Enhanced Multiply-Accumulate Unit (EMAC) Figure 3-7 and Figure 3-8 show relative alignment of input operands, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats. OperandY X Product 32 OperandX 32 0 23 40 Extended Product 8 40 8 40 + Accumulator 8 Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0] Figure 3-7.
Enhanced Multiply-Accumulate Unit (EMAC) Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions have an effective issue rate of 1 cycle, regardless of input operand size or type. All arithmetic operations use register-based input operands, and summed values are stored in an accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose register.
Enhanced Multiply-Accumulate Unit (EMAC) • If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0). — If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up. — If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down. This method minimizes rounding bias and creates as statistically correct an answer as possible.
Enhanced Multiply-Accumulate Unit (EMAC) movem.l move.l move.l move.l move.l move.l move.l move.l move.l move.l (a7),#0x00ff #0,macsr d0,acc0 d1,acc1 d2,acc2 d3,acc3 d4,accext01 d5,accext23 d6,mask d7,macsr ; restore the state from memory ; disable rounding in the macsr ; restore the accumulators ; restore the accumulator extensions ; restore the address mask ; restore the macsr Executing this sequence type can correctly save and restore the exact state of the EMAC programming model. 3.3.1.
Enhanced Multiply-Accumulate Unit (EMAC) Table 3-8. EMAC Instruction Summary (continued) Command Mnemonic Description Load Accumulator Extensions 23 move.l {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit operand Store Accumulator Extensions 01 move.l ACCext01,Rx Writes the contents of accumulator 0,1 extension bytes into a CPU register Store Accumulator Extensions 23 move.l ACCext23,Rx Writes the contents of accumulator 2,3 extension bytes into a CPU register 3.3.
Enhanced Multiply-Accumulate Unit (EMAC) As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. A major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between accumulator(s) and general-purpose registers. 3.3.
Enhanced Multiply-Accumulate Unit (EMAC) • The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed.
Enhanced Multiply-Accumulate Unit (EMAC) /* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {product[39], product[39:1]} break; } if (MACSR.
Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1 /* check for product rounding */ if (MACSR.
Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */ MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC and and MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.
Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; } MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Enhanced Multiply-Accumulate Unit (EMAC) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 4 Cache 4.1 Introduction This chapter describes cache operation on the ColdFire processor. 4.1.1 Features Features include the following: • Configurable as instruction, data, or split instruction/data cache • 2-Kbyte direct-mapped cache • Single-cycle access on cache hits • Physically located on the ColdFire core's high-speed local bus • Nonblocking design to maximize performance • Separate instruction and data 16-Byte line-fill buffers • Configurable instruction cache miss-fetch algorithm 4.
Cache output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access in a single cycle. The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded into the cache. The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated line fill buffer are examined.
Cache of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC instruction with an Rc value of 0x002, 0x004 and 0x005, respectively. Table 4-1. Cache Memory Map BDM1 Register Width (bits) Access2 Reset Value Section/Page 0x002 Cache Control Register (CACR) 32 W 0x0000_0000 4.2.1/4-3 0x004 Access Control Register 0 (ACR0) 32 W See Section 4.2.2/4-6 0x005 Access Control Register 1 (ACR1) 32 W See Section 4.2.
Cache Table 4-2. CACR Field Descriptions (continued) Field Description 28 CPDI Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits [10:4] of the address is invalidated if CPDI is cleared. If CPDI is set, no operation is performed. 0 Enable invalidation 1 Disable invalidation 27 CFRZ Cache freeze. This field allows the user to freeze the contents of the cache.
Cache Table 4-2. CACR Field Descriptions (continued) Field Description 9 DCM Default cache mode. This bit defines the default cache mode. For more information on the selection of the effective memory attributes, see Section 4.3.2, “Memory Reference Attributes. 0 Caching enabled 1 Caching disabled 8 DBWE Default buffered write enable. This bit defines the default value for enabling buffered writes.
Cache Table 4-4. Cache Invalidate All as Defined by CACR 4.2.
Cache Table 4-5. ACRn Field Descriptions Field Description 31–24 AB Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR. 23–16 AM Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison is ignored. 15 EN ACR Enable.
Cache If the referenced address is mapped into the SRAM module, that module services the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion. 4.3.
Cache 4.3.5 Cache Miss Fetch Algorithm/Line Fills As discussed in Section 4.1.2, “Introduction,” the cache hardware includes a 16-byte, line-fill buffer for providing temporary storage for the last fetched line. With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in the tag memory and the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16 bytes.
Cache For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction fetch is processed, as defined by Table 4-7. For this condition, the line-fill buffer is loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory array. Table 4-7 shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch.
Chapter 5 Static RAM (SRAM) 5.1 • • • • • 5.2 SRAM Features One 64-Kbyte SRAM Single-cycle access Physically located on processor's high-speed local bus Memory location programmable on any 0-modulo-64 Kbyte address Byte, word, longword address capabilities SRAM Operation The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the 4-GByte address space.
Static RAM (SRAM) The RAMBAR contains several control fields. These fields are shown in Figure 5-1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Reset Undefined R/W W 15 14 Field 13 — 12 11 10 9 8 PRI1 PRI2 SPV Reset 7 WP 6 — 5 4 3 2 1 0 C/I SC SD UC UD V Undefined R/W 0 W Address CPU + 0xC05 Figure 5-1. SRAM Base Address Register (RAMBAR) Table 5-1.
Static RAM (SRAM) Table 5-1. SRAM Base Address Register (continued) Bits Name Description 5–1 C/I, SC, SD, UC, UD Address space masks (ASn) These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the SRAM module.
Static RAM (SRAM) The following loop initializes the entire SRAM to zero lea.l RAMBASE,A0 ;load pointer to SRAM move.l #16384,D0 ;load loop counter into D0 clr.l (A0)+) ;clear 4 bytes of SRAM subq.l #1,D0 ;decrement loop counter bne.b SRAM_INIT_LOOP ;if done, then exit; else continue looping SRAM_INIT_LOOP: 5.3.
Chapter 6 ColdFire Flash Module (CFM) The MCF5282 incorporates SuperFlash® technology licensed from SST. The ColdFire Flash Module (CFM) is constructed with eight banks of 32K x 16-bit Flash to generate a 512-Kbyte, 32-bit wide electrically erasable and programmable read-only memory array. The CFM is ideal for program and data storage for single-chip applications and allows for field reprogramming without external high-voltage sources.
ColdFire Flash Module (CFM) 6.2 Block Diagram The CFM module shown in Figure 6-1 contains the Flash physical blocks, the ColdFire Flash bus and IP bus interfaces, Flash interface, register blocks, and the BIST engine. Each 128-Kbyte Flash physical block is arranged as two 32,768-word (16 bits) memory arrays. Each of these memory arrays is designated as xH or xL, where x represents one of the four Flash physical blocks (0–3) and H/L represents the high or low 16 bits of each longword of logical memory.
ColdFire Flash Module (CFM) Internal Bus Memory Array Block 0H 32K x 16 Flash Physical Block 3 Memory Array Block 0L 32K x 16 SATO SATO • • • Flash Physical Block 0 Memory Array Block 3H 32K x 16 SATO Memory Array Block 3L 32K x 16 SATO Flash Interface BIST Engine Flash Control Registers VDDF VSSF Backdoor Access Note: Mass Erase Block 0 (256 Kbytes) = Flash Physical Block 0 and Flash Physical Block 1.
ColdFire Flash Module (CFM) 6.3 Memory Map Figure 6-2 shows the memory map for the CFM array. The CFM array can reside anywhere in the memory space of the MCU. The starting address of the array is determined by the CFM array base address which must reside on a natural size boundary; that is, the CFM array base address must be an integer multiple of the array size. The CFM register space must reside on a 64 byte boundary as determined by the CFM register base address.
ColdFire Flash Module (CFM) 6.3.1 CFM Configuration Field The CFM configuration field comprises 24 bytes of reserved array memory space that determines the module protection and access restrictions out of reset. Data to secure the Flash from unauthorized access is also stored in the CFM configuration field. Table 6-1 describes each byte used in this field. Table 6-1.
ColdFire Flash Module (CFM) NOTE Flash accesses (reads/writes) by a bus master other than the core, (DMA controller or Fast Ethernet Controller), or writes to Flash by the core during programming must use the backdoor Flash address of IPSBAR plus an offset of 0x0400_0000. For example, for a DMA transfer from the first location of Flash when IPSBAR is still at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000.
ColdFire Flash Module (CFM) Table 6-2. FLASHBAR Field Descriptions Bits Name 31–19 BA[31:18] 18–9 — 8 WP 7–6 — 5–1 Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space. Reserved, should be cleared. Write protect. Read only. Allows only read accesses to the Flash.
ColdFire Flash Module (CFM) Table 6-3. CFM Register Address Map IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Access1 Bits 7–0 0x1D_0014 CFMSACC S 0x1D_0018 CFMDACC S 0x1D_001C 2 S Reserved 0x1D_0020 CFMUSTAT Reserved2 S 0x1D_0024 CFMCMD Reserved2 S 1 S = Supervisor access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
ColdFire Flash Module (CFM) Table 6-4. CFMCR Field Descriptions Bits Name Description 7 CBEIE Command buffer empty interrupt enable. The CBEIE bit is readable and writable. CBEIE enables an interrupt request when the command buffer for the Flash physical blocks is empty. 1 Request an interrupt whenever the CBEIF flag is set. 0 Command buffer empty interrupts disabled 6 CCIE 5 KEYACC 4–0 — 6.3.4.2 Command complete interrupt enable. The CCIE bit is readable and writable.
ColdFire Flash Module (CFM) NOTE CFMCLKD must be written with an appropriate value before programming or erasing the Flash array. Refer to Section 6.4.3.1, “Setting the CFMCLKD Register.” 6.3.4.3 CFM Security Register (CFMSEC) The CFMSEC controls the Flash security features. NOTE Enabling Flash security will disable BDM communications. NOTE When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration.
ColdFire Flash Module (CFM) Table 6-6. CFMSEC Field Descriptions Bits Name 29–16 — 15–0 SEC[15:0] Description Reserved. Should be cleared. Security field. The SEC bits define the security state of the device; see below.
ColdFire Flash Module (CFM) 6.3.4.4 CFM Protection Register (CFMPROT) The CFMPROT specifies which Flash logical sectors are protected from program and erase operations. 31 16 Field PROT Reset See Note R/W R/W 15 0 Field PROT Reset See Note R/W R/W Address IPSBAR + 0x1D_0010 Note: The CFMPROT register is loaded at reset from the Flash Program/Erase Sector Protection longword stored at the array base address + 0x0000_0400. Figure 6-7.
ColdFire Flash Module (CFM) (ARRAY_BASE + 0x0007_FFFF) SECTOR 31 PROTECT[31] (ARRAY_BASE + 0x0007_C000) • • • PROTECT[2] } 16Kbyte Sector SECTOR 2 Protected Flash Logical Sectors as defined by CFMPROT register (ARRAY_BASE + 0x0000_8000) SECTOR 1 (ARRAY_BASE + 0x0000_4000) SECTOR 0 (ARRAY_BASE + 0x0000_0000) Figure 6-8. CFMPROT Protection Diagram 6.3.4.5 CFM Supervisor Access Register (CFMSACC) The CFMSACC specifies the supervisor/user access permissions of Flash logical sectors.
ColdFire Flash Module (CFM) Table 6-8. CFMSACC Field Descriptions Bits Name Description 31–0 SUPV[31:0] Supervisor address space assignment. The SUPV[31:0] bits are always readable and only writable when LOCK = 0. Each Flash logical sector can be mapped into supervisor or unrestricted address space. CFMSACC uses the same correspondence between logical sectors and register bits as does CFMPROT. See Figure 6-8 for details.
ColdFire Flash Module (CFM) 6.3.4.7 CFM User Status Register (CFMUSTAT) The CFMUSTAT reports Flash state machine command status, array access errors, protection violations, and blank check status. Field 7 6 CBEIF CCIF Reset 5 1 PVIOL ACCERR — BLANK 0 — 1100_0000 R/W R/W Address R R/W IPSBAR + 0x1D_0020 Figure 6-11. CFM User Status Register (CFMUSTAT) NOTE Only one CFMUSTAT bit should be cleared at a time. Table 6-10.
ColdFire Flash Module (CFM) Table 6-10. CFMUSTAT Field Descriptions Bits Name Description 2 BLANK Erase Verified Flag. The BLANK flag indicates that the erase verify command (RDARY1) has checked the two interleaved Flash physical blocks and found them to be blank. Clear BLANK by writing it to 1. Writing a 0 has no effect. 1 Flash physical blocks verify as erased. 0 If an erase verify command has been requested, and the CCIF flag is set, then the selected Flash physical blocks are not blank.
ColdFire Flash Module (CFM) initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug modes and when the MCU boots in master mode or emulation mode. 6.4.1 Read Operations A valid read operation occurs whenever a transfer request is initiated by the ColdFire core, the address is equal to an address within the valid range of the CFM memory space, and the read/write control indicates a read cycle.
ColdFire Flash Module (CFM) fSYS fCLK = 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) Consider the following example for fSYS = 66 MHz: DIV[5:0] = = fSYS 2 x 200kHz x (1 + (PRDIV8 x 7)) 66 MHz 400 kHz x (1 + (1 x 7)) = 20 fSYS fCLK = 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) = 66 MHz 2 x (20 + 1) x (1 + (1 x 7)) = 196.43 kHz So, for fSYS = 66 MHz, writing 0x54 to CFMCLKD will set fCLK to 196.43 kHz which is a valid frequency for the timing of program and erase operations.
ColdFire Flash Module (CFM) NOTE The page erase command operates simultaneously on adjacent erase pages in two interleaved Flash physical blocks. Thus, a single erase page is effectively 2 Kbyte. 2. Write the program, erase, or verify command to CFMCMD, the command buffer. See Section 6.4.3.3, “Flash Valid Commands.” 3. Launch the command by writing a 1 to the CBEIF flag. This clears CBEIF. When command execution is complete, the Flash state machine sets the CCIF flag.
ColdFire Flash Module (CFM) START READ CFMCLKD CLOCK REGISTER WRITTEN CHECK NO DIVLD SET? YES WRITE CFMCLKD READ CFMUSTAT CBEIF SET? NO YES 1. WRITE PROGRAM DATA TO ARRAY ADDRESS 2. WRITE PROGRAM COMMAND 0x20 TO CFMCMD NOTE: COMMAND SEQUENCE ABORTED BY WRITING 0x00 TO CFMUSTAT 3.
ColdFire Flash Module (CFM) 6.4.3.4 Flash User Mode Illegal Operations The ACCERR flag will be set during a command write sequence if any of the illegal operations below are performed. Such operations will cause the command sequence to immediately abort. 1. Writing to the CFM array before initializing CFMCLKD. 2. Writing to the CFM array while in emulation mode. 3. Writing a byte or a word to the CFM array. Only 32-bit longword programming is allowed. 4. Writing to the CFM array while CBEIF is not set.
ColdFire Flash Module (CFM) 6.4.5 Master Mode If the MCU is booted in master mode with an external memory selected as the boot device, the CFM will not respond to the first transfer request out of reset. This will allow the external boot device to provide the reset vector and terminate the bus cycle. 6.5 Flash Security Operation The CFM array provides security information to the integration module and the rest of the MCU. A longword in the Flash configuration field stores this information.
ColdFire Flash Module (CFM) 6.5.1 Back Door Access If the KEYEN bit is set, security can be bypassed by: 1. Setting the KEYACC bit in the CFM configuration register (CFMMCR). 2. Writing the correct 8-byte back door comparison key to the CFM array at addresses 0x0000_0400 to 0x0000_0407. This operation must consist of two 32-bit writes to address 0x0000_0400 and 0x0000_0404 in that order. The two back door write cycles can be separated by any number of bus cycles. 3. Clearing the KEYACC bit. 4.
ColdFire Flash Module (CFM) Table 6-14. CFM Interrupt Sources (continued) Interrupt Source Interrupt Flag Local Enable All commands are completed CCIF (CFMUSTAT) CCIE (CFMCR) Access error ACCERR (CFMUSTAT) AEIE (CFMCR) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 7 Power Management The power management module (PMM) controls the device’s low-power operation. 7.1 Features The following features support low-power operation. • Four modes of operation: — Run — Wait — Doze — Stop • Ability to shut down most peripherals independently • Ability to shut down the external CLKOUT pin 7.2 Memory Map and Registers This subsection provides a description of the memory map and registers. 7.2.
Power Management 7.2.2 Memory Map Table 7-1. Chip Configuration Module Memory Map IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0 Access1 0x0000_0010 Core Reset Status Register (CRSR)2 Core Watchdog Control Register (CWCR) Low-Power Interrupt Control Register (LPICR) Core Watchdog Service Register (CWSR) S 0x0011_0004 Chip Configuration Register (CCR)3 Reserved Low-Power Control Register (LPCR) S 1 S = CPU supervisor mode access only.
Power Management NOTE Only fixed (external) interrupt can bring a device out of stop mode. To exit from other low-power modes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in that particular low-power mode. 5. Once an appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the SIM responds by asserting the request to exit low-power mode. 6.
Power Management 7.2.3.2 Low-Power Control Register (LPCR) The LPCR controls chip operation and module operation during low-power modes. 7 Field 6 LPMD 5 — Reset 4 3 STPMD 2 1 0 — LVDSE — 0000_0010 R/W R/W Address IPSBAR + 0x0011_0007 Figure 7-2. Low-Power Control Register (LPCR) Table 7-4. LPCR Field Descriptions Bits Name Description 7–6 LPMD Low-power mode select. Used to select the low-power mode the chip enters once the ColdFire CPU executes the STOP instruction.
Power Management Table 7-6. PLL/CLKOUT Stop Mode Operation Operation During Stop Mode STPMD[1:0] System Clocks CLKOUT PLL OSC PMM 00 Disabled Enabled Enabled Enabled Enabled 01 Disabled Disabled Enabled Enabled Enabled 10 Disabled Disabled Disabled Enabled Enabled 11 Disabled Disabled Disabled Disabled Low-Power Option NOTE If LPCR[LPMD] is cleared, then the device stops executing code upon issue of a STOP instruction. However, no clocks are disabled. 7.
Power Management 7.3.1.2 Wait Mode Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode. 7.3.1.3 Doze Mode Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines individual operational characteristics in doze mode.
Power Management 7.3.2.3 Flash The Flash module is in a low-power state if not being accessed. No recovery time is required after exit from any low-power mode. The MCF5280 does not have a Flash module. 7.3.2.4 System Control Module (SCM) The SCM’s core Watchdog timer can bring the device out of all low-power modes except stop mode. In stop mode, all clocks stop, and the core Watchdog does not operate. When enabled, the core Watchdog can bring the device out of low-power mode in one of two ways.
Power Management 7.3.2.8 UART Modules (UART0, UART1, and UART2) In wait and doze modes, the UART may generate an interrupt to exit the low-power modes. • Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions. • The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode. In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down.
Power Management 7.3.2.12 Interrupt Controllers (INTC0, INTC1) The interrupt controller is not affected by any of the low-power modes. All logic between the input sources and generating the interrupt to the processor will be combinational to allow the ability to wake up the CPU processor during low-power stop mode when all system clocks are stopped.
Power Management 7.3.2.17 Clock Module In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop mode, all clocks to the system will be stopped. During stop mode, there are several options for enabling/disabling the PLL and/or crystal oscillator (OSC); each of these options requires a compromise between wakeup recovery time and stop mode power.
Power Management 7.3.2.21 Queued Analog-to-Digital Converter (QADC) Setting the queued analog-to-digital converter (QADC) stop bit (QSTOP) will disable the QADC. The QADC is unaffected by either wait or doze mode and may generate an interrupt to exit these modes. Low-power stop mode (or setting the QSTOP bit), immediately freezes operation, register values, state machines, and external pins.
Power Management • Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, then upon detection of recessive to dominant transition on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks.
Power Management • • No host access to the FlexCAN module. The FlexCAN is neither in halt mode (MCR bit 8), in stop mode (MCT bit 15), nor in BUSOFF. 7.3.2.24 ColdFire Flash Module The ColdFire Flash Control Module is capable of generating interrupts by the setting of the CBEIF or CCIF bits in the CFMUSTAT. These interrupt sources, however, should not occur when the device is in a low-power mode as long as no Flash operation was in progress when the low-power mode was entered.
Power Management Table 7-7.
Power Management 4 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Power Management MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 8 System Control Module (SCM) This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core watchdog timer (CWT), and the system control registers and logic.
System Control Module (SCM) 8.3 Memory Map and Register Definition The memory map for the SCM registers is shown in Table 8-1. All the registers in the SCM are memory-mapped as offsets within the 1 Gbyte IPS address space and accesses are controlled to these registers by the control definitions programmed into the SACU. Table 8-1. SCM Register Map IPSBAR Offset [31:24] [23:16] 0x00_0000 IPSBAR 0x00_0004 — 0x00_0008 RAMBAR 0x00_000C — 0x00_0010 CRSR CWCR 0x00_0018 8.4.
System Control Module (SCM) 5. Chip Selects NOTE This is the list of memory access priorities when viewed from the processor core. See Figure 8-1 and Table 8-2 for descriptions of the bits in IPSBAR. 31 30 29 16 Field BA31 BA30 Reset 0 — 1 — R/W R/W 15 1 0 Field — V Reset — 1 R/W R/W Address IPSBAR + 0x000 Figure 8-1. IPS Base Address Register (IPSBAR) Table 8-2. IPSBAR Field Description Bits Name Description 31–30 BA Base address.
System Control Module (SCM) The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a 0-modulo-size value.
System Control Module (SCM) 8.4.3 Core Reset Status Register (CRSR) The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last type of reset that occurred. The CRSR is updated by the control logic when the reset is complete. Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect.
System Control Module (SCM) When the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, an internal reset is asserted and CRSR[CWDR] is set. To prevent the core watchdog timer from interrupting or resetting, the CWSR must be serviced by performing the following sequence: 1. Write 0x55 to CWSR. 2. Write 0xAA to the CWSR. Both writes must occur in order before the time-out, but any number of instructions can be executed between the two writes.
System Control Module (SCM) Table 8-5. CWCR Field Description (continued) 5–3 2 1 0 8.4.5 CWT[2:0] CWTA Core watchdog timing delay. These bits select the timeout period for the CWT. At system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is disabled (CWCR[CWE] = 0).
System Control Module (SCM) “back door” to SRAM and Flash SRAM1 MPARK RAMBAR CPU M0 DMA M2 Internal Bus Master M1 EIM MARB Internal Modules FEC SDRAMC *Not used on MCF5214/16 M3 Figure 8-6. Arbiter Module Functions 8.5.1 Overview The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the following attributes: • The master pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available.
System Control Module (SCM) 8.5.2 Arbitration Algorithms There are two modes of arbitration: fixed and round-robin. This section discusses the differences between them. 8.5.2.1 Round-Robin Mode Round-robin arbitration is the default mode after reset. This scheme cycles through the sequence of masters as specified by MPARK[Mn_PRTY] bits. Upon completion of a transfer, the master is given the lowest priority and the priority for all other masters is increased by one.
System Control Module (SCM) 31 26 Field — 25 23 22 21 20 19 18 17 16 M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTY Reset 0011_0000_1110_0001 R/W Field 24 R/W 15 14 — FIXED Reset 13 12 TIMEOUT PRKLAST 11 8 7 LCKOUT_TIME 0 — 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x01C Figure 8-7. Default Bus Master Park Register (MPARK) Table 8-6.
System Control Module (SCM) Table 8-6. MPARK Field Description (continued) Bits Name 14 FIXED 13 TIMEOUT Timeout Enable 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached.
System Control Module (SCM) 8.6.2 Features Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes: • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write • User instruction fetch • User operand read • User operand write Instruction fetch accesses are associated with the execute attribute.
System Control Module (SCM) Table 8-7. SACU Register Memory Map IPSBA R Offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] — — — — — — 0x020 MPR 0x024 PACR0 PACR1 PACR2 PACR3 0x028 PACR4 — PACR5 PACR6 0x02c PACR7 — PACR8 — 0x030 GPACR0 GPACR1 — — 0x034 — — — — 0x038 — — — — 0x03C — — — — 8.6.3.1 Master Privilege Register (MPR) The MPR specifies the access privilege level associated with each bus master in the platform.
System Control Module (SCM) and writes. Each PACR follows the format illustrated in Figure 8-9. For a list of PACRs and the modules that they control, refer to Table 8-11. 7 Field 6 4 LOCK1 3 ACCESS_CTRL1 Reset 2 LOCK0 0 ACCESS_CTRL0 0000_0000 R/W R/W Address IPSBAR + 0x24 + Offset Figure 8-9. Peripheral Access Control Register (PACRn) Table 8-9. PACR Field Descriptions Bits Name Description 7 LOCK1 This bit, when set, prevents subsequent writes to ACCESSCTRL1.
System Control Module (SCM) Table 8-11. Peripheral Access Control Registers (PACRs) (continued) Modules Controlled IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 PACR3 UART2 — 0x028 PACR4 2 I C QSPI 0x029 — — — 0x02a PACR5 DTIM0 DTIM1 0x02b PACR6 DTIM2 DTIM3 0x02c PACR7 INTC0 INTC1 0x02d — — — 0x02e PACR8 FEC0 — 0x027 At reset, these on-chip modules are configured to have only supervisor read/write access capabilities.
System Control Module (SCM) Table 8-12. GPACR Field Descriptions Bits Name Description 7 LOCK This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. 6–4 — 3–0 Reserved, should be cleared. ACCESS_CTRL This 4-bit field defines the access control for the given memory region. The encodings for this field are shown in Table 8-13.
System Control Module (SCM) Table 8-14. GPACR Address Space Register Space Protected (IPSBAR Offset) Modules Protected GPACR0 0x0000_0000– 0x03FF_FFFF Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) GPACR1 0x0400_0000– 0x07FF_FFFF CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) Note: Reserved for the MCF5280 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
System Control Module (SCM) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 9 Clock Module The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly.
Clock Module 9.3 Low-power Mode Operation This subsection describes the operation of the clock module in low-power and halted modes of operation. Low-power modes are described in Chapter 7, “Power Management.” Table 9-1 shows the clock module operation in low-power modes. Table 9-1.
Clock Module . CLKMOD[1:0] EXTAL CLKOUT LOCKS XTAL EXTERNAL CLOCK RSTOUT MFD PLLMODE LOCK REFERENCE CLOCK LOCS PLL OSC RFD[2:0] TO RESET MODULE PLLREF LOCEN LOLRE LOCRE PLL CLOCK OUT STPMD[1:0] SCALED PLL CLOCK OUT STOP MODE CLKGEN INTERNAL CLOCK PLLSEL CLKOUT DISCLK INTERNAL CLOCKS STOP MODE PLLMODE LOCK FWKUP Figure 9-1. Clock Module Block Diagram MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Clock Module CLKMOD[1:0] RSTOUT STPMD LOCKS LOCK DETECT LOCK LOLRE TO RESET MODULE PLLMODE LOCEN LOCRE LOSS OF CLOCK DETECT REFERENCE CLOCK LOCS PHASE AND FREQUENCY DETECT CHARGE PUMP FILTER VCO RFD[2:0] SCALED PLL CLOCK OUT PLLSEL DISCLK MDF[2:0] CLKOUT ÷ MFD (4–18) PLL CLOCK OUT Figure 9-2. PLL Block Diagram 9.5 Signal Descriptions The clock module signals are summarized in Table 9-2 and a brief description follows.
Clock Module 9.5.2 XTAL This output is an internal oscillator connection to the external crystal. 9.5.3 CLKOUT This output reflects the internal system clock. 9.5.4 CLKMOD[1:0] These inputs are used to select the clock mode during chip configuration. 9.5.5 RSTOUT The RSTOUT pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset control status register (RCR); see Section 29.4.1, “Reset Control Register (RCR).” 9.
Clock Module 9.6.2 Register Descriptions This subsection provides a description of the clock module registers. 9.6.2.1 Synthesizer Control Register (SYNCR) Field 15 14 13 12 11 10 9 8 LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 Reset 0010_0001 R/W Field R/W 7 6 5 4 3 2 1 0 LOCEN DISCLK FWKUP — STPMD1 STPMD0 — — Reset 0000_0000 R/W R/W Address R R/W R IPSBAR + 0x0012_0000 Figure 9-3. Synthesizer Control Register (SYNCR) Table 9-4.
Clock Module Table 9-4. SYNCR Field Descriptions (continued) Bit(s) Name Description 14–12 MFD Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one. Note: In external clock mode, the MFD[2:0] bits have no effect.
Clock Module Table 9-4. SYNCR Field Descriptions (continued) Bit(s) Name 7 LOCEN Enables the loss-of-clock function. LOCEN does not affect the loss of lock function. 1 Loss-of-clock function enabled 0 Loss-of-clock function disabled Note: In external clock mode, the LOCEN bit has no effect. 6 DISCLK Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low.
Clock Module Table 9-5. SYNSR Field Descriptions Bit(s) Name Description 7 PLLMODE Clock mode bit. The PLLMODE bit is configured at reset and reflects the clock mode as shown in Table 9-6. 1 PLL clock mode 0 External clock mode 6 PLLSEL PLL select. Configured at reset and reflects the PLL mode as shown in Table 9-6. 1 Normal PLL mode 0 1:1 PLL mode 5 PLLREF PLL reference. Configured at reset and reflects the PLL reference source in normal PLL mode as shown in Table 9-6.
Clock Module Table 9-5. SYNSR Field Descriptions (continued) Bit(s) Name Description 2 LOCS Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks are operating normally. LOCS = 1 when system clocks have failed due to a reference failure or PLL failure.
Clock Module 1 fref = input reference frequency fsys = CLKOUT frequency MFD ranges from 0 to 7. RFD ranges from 0 to 7. CAUTION XTAL must be tied low in external clock mode when reset is asserted. If it is not, clocks could be suspended indefinitely. The external clock is divided by two internally to produce the system clocks. 9.7.2 Clock Operation During Reset In external clock mode, the system is static and does not recognize reset until a clock is applied to EXTAL.
Clock Module The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation. Figure 9-5 shows the external support circuitry for the crystal oscillator with example component values. Actual component values depend on crystal specifications. The following subsections describe each major block of the PLL. Refer to Figure to see how these functional sub-blocks interact.
Clock Module The feedback clock comes from one of the following: • CLKOUT in 1:1 PLL mode • VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode • VCO output divided by the MFD in normal PLL mode When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the PFD pulses the UP signal.
Clock Module The lock detect function uses two counters. One is clocked by the reference and the other is clocked by the PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the PLL has achieved frequency lock.
Clock Module 9.7.4.7 PLL Loss of Lock Reset If the LOLRE bit in the SYNCR is set, a loss of lock condition asserts reset. Reset reinitializes the LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register (RSR) to determine if a loss of lock caused the reset. See Section 29.4.2, “Reset Status Register (RSR).” To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. In external clock mode, the PLL cannot lock.
Clock Module A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the PLL must be functioning properly to exit reset. 9.7.4.
Clock Module NRM NRM NRM 0 0 0 Off On 0 Lose lock 0 0 0 Off On 1 Lose lock 0 0 0 On On 0 MODE Out NRM Lose reference clock or no lock regain Stuck Lose reference clock, regain NRM ‘LK 1 ‘LC Block LOCKS from being cleared No lock regain Unstable NRM 0–>‘L K 0–> 1 ‘LC Block LOCKS until lock regained Lose reference clock or no f.b.
Clock Module NRM 0 0 1 On On X — — MODE Out NRM ‘LK Lose lock or clock RESET NRM NRM NRM NRM NRM 1 0 0 Off Off 0 Lose lock, f.b. clock, reference clock 1 0 0 Off On 0 Lose lock, f.b. clock 1 0 0 Off On 1 Lose lock, f.b. clock 1 0 0 On On 0 1 0 0 On On 1 — — — ‘LC — — No regain Stuck Regain NRM No f.b. clock or lock regain Stuck Lose reference clock SCM 0 0 1 Wakeup without lock Regain f.b. clock Unstable NRM 0–>‘L K 0–> 1 ‘LC REF mode not entered during stop No f.b.
Clock Module NRM 1 0 1 On On X NRM 1 1 X Off X NRM 1 1 0 On On 0 NRM NRM — — X Lose lock, f.b.
Clock Module SCM 1 0 0 On On 1 — — Lose reference clock MODE Out SCM 0 0 LOCS PLL Action During Stop LOCK Expected PLL Action at Stop LOCKSS FWKUP OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 5 of 5) Comments 1 SCM Note: PLL = PLL enabled during STOP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = Oscillator enabled during STOP mode.
Chapter 10 Interrupt Controller Modules This section details the functionality for the interrupt controllers (INTC0, INTC1).
Interrupt Controller Modules Section 2.3.3.1, “Exception Stack Frame Definition” for more information on the stack frame format). After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine.
Interrupt Controller Modules Table 10-1.
Interrupt Controller Modules 10.1.1.2 Interrupt Prioritization As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The decoded priority levels from all the interrupt controllers are logically summed together and the highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase. 10.1.1.
Interrupt Controller Modules The registers and their locations are defined in Table 10-3. The offsets listed start from the base address for each interrupt controller. The base addresses for the interrupt controllers are listed below: Table 10-2. Interrupt Controller Base Addresses 1 Interrupt Controller Number Base Address INTC0 IPSBAR + 0xC00 INTC1 IPSBAR + 0xD00 Global IACK Registers Space1 IPSBAR + 0xF00 This address space only contains the L1ACK-L7IACK registers. See Section 10.3.
Interrupt Controller Modules Table 10-3. Interrupt Controller Memory Map (continued) Module Offset Bits[31:24] Bits[23:16] 0x80–0xDC 10.3 Bits[15:8] Bits[7:0] Reserved 0xE0 SWIACK Reserved 0xE4 L1IACK Reserved 0xE8 L2IACK Reserved 0xEC L3IACK Reserved 0xF0 L4IACK Reserved 0xF4 L5IACK Reserved 0xF8 L6IACK Reserved 0xFC L7IACK Reserved Register Descriptions 10.3.
Interrupt Controller Modules Table 10-4. IPRHn Field Descriptions Bits Name 31–0 INT Description Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRHn samples the signal generated by the interrupting source. The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set.
Interrupt Controller Modules . 31 16 Field INT_MASK[63:48] Reset 1111_1111_1111_1111 R/W R/W 15 0 Field INT_MASK[47:32] Reset 1111_1111_1111_1111 R/W R/W IPSBAR + 0xC08, 0xD08 Figure 10-3. Interrupt Mask Register High (IMRHn) Table 10-6. IMRHn Field Descriptions Bits Name Description 31–0 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt.
Interrupt Controller Modules Table 10-7. IMRLn Field Descriptions Bits Name Description 31–1 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set. 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked 0 MASKALL Mask all interrupts.
Interrupt Controller Modules 31 16 Field INTFRCH[63:48] Reset 0000_0000_0000_0000 R/W R/W 15 0 Field INTFRCH[47:32] Reset 0000_0000_0000_0000 R/W R/W IPSBAR + 0xC10, 0xD10 Figure 10-5. Interrupt Force Register High (INTFRCHn) Table 10-8. INTFRCHn Field Descriptions Bits 31–0 Name Description INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
Interrupt Controller Modules 10.3.4 Interrupt Request Level Register (IRLRn) This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output is combined with similar outputs from INTC1 and eventually encoded into the 3-bit priority interrupt level driven to the processor core.
Interrupt Controller Modules Table 10-11. IACKLPRn Field Descriptions (continued) Bits Name 6–4 LEVEL 3–0 PRI 10.3.6 Description Interrupt level. Represents the interrupt level currently being acknowledged. Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged.
Interrupt Controller Modules 10.3.6.1 Interrupt Sources Table 10-13 and Table 10-14 list the interrupt sources for each interrupt request line for INTC0 and INTC1. Table 10-13.
Interrupt Controller Modules Table 10-13.
Interrupt Controller Modules Table 10-13.
Interrupt Controller Modules Table 10-14.
Interrupt Controller Modules service routine, and if there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to the appropriate service routine, but without taking another interrupt exception. When the interrupt controller receives a software IACK read, it returns the vector number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller.
Interrupt Controller Modules NOTE The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0–6. • Second, the processor executes a STOP instruction which places it in stop mode.
Chapter 11 Edge Port Module (EPORT) 11.1 Introduction The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 11-1.
Edge Port Module (EPORT) Table 11-1. Edge Port Module Operation in Low-power Modes Low-power Mode EPORT Operation Mode Exit Wait Normal Any IRQx Interrupt at or above level in LPICR Doze Normal Any IRQx Interrupt at or above level in LPICR Stop Level-sensing Only Any IRQx Interrupt set for level-sensing at or above level in LPICR In wait and doze modes, the EPORT module continues to operate as it does in run mode.
Edge Port Module (EPORT) 11.4 Memory Map and Registers This subsection describes the memory map and register structure. 11.4.1 Memory Map Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of 0x0013_0000. Table 11-2.
Edge Port Module (EPORT) Table 11-3. EPPAR Field Descriptions Bit(s) Name Description 15–2 EPPAx EPORT pin assignment select fields. The read/write EPPAx fields configure EPORT pins for level detection and rising and/or falling edge detection. Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid interrupt request. Level-sensitive interrupt inputs are not latched.
Edge Port Module (EPORT) 11.4.2.3 Edge Port Interrupt Enable Register (EPIER) Field 7 6 5 4 3 2 1 0 EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 — Reset 0000_0000 R/W R/W Address R IPSBAR + 0x0013_0003 Figure 11-4. EPORT Port Interrupt Enable Register (EPIER) Table 11-5. EPIER Field Descriptions Bit(s) Name Description 7–1 EPIEx Edge port interrupt enable bits enable EPORT interrupt requests.
Edge Port Module (EPORT) 11.4.2.5 Edge Port Pin Data Register (EPPDR) Field 7 6 5 4 EPPD7 EPPD6 EPPD5 EPPD4 Reset 3 2 1 0 EPPD3 EPPD2 EPPD1 Current pin state R/W — 0 R Address IPSBAR + 0x0013_0005 Figure 11-6. EPORT Port Pin Data Register (EPPDR) Table 11-7. EPPDR Field Descriptions Bit(s) Name Description 7–1 EPPDx Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7–IRQ1.
Chapter 12 Chip Select Module This chapter describes the chip select module, including the operation and programming model of the chip select registers, which include the chip select address, mask, and control registers. NOTE Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 12.
Chip Select Module Table 12-2.
Chip Select Module 12.3 Chip Select Operation Each chip select has a dedicated set of registers for configuration and control. • Chip select address registers (CSARn) control the base address of the chip select. See Section 12.4.1.1, “Chip Select Address Registers (CSAR0–CSAR6)”. • Chip select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 12.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR6)”.
Chip Select Module between the data bus and the external byte strobe control lines (BS[3:0]). Note that all byte lanes are driven, although the state of unused byte lanes is undefined. External data bus BS3 BS2 BS1 BS0 D[31:24] D[23:16] D[15:8] D[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 Byte 2 Byte 1 Byte 3 Driven, undefined 32-bit port memory 16-bit port memory 8-bit port memory Byte 0 Byte 1 Byte 2 Byte 3 Driven, undefined Figure 12-1. Connections for External Memory Port Sizes 12.3.
Chip Select Module Table 12-5. Chip Select Registers IPSBAR Offset 0x00_0080 [31:24] [23:16] Chip select address register—bank 0 (CSAR0) [p. 12-6] 0x00_0084 [15:8] [7:0] Reserved1 Chip select mask register—bank 0 (CSMR0) [p. 12-6] 0x00_0088 Reserved1 Chip select control register—bank 0 (CSCR0) [p. 12-7] 0x00_008C Chip select address register—bank 1 (CSAR1) [p. 12-6] Reserved1 0x00_0090 Chip select mask register—bank 1 (CSMR1) [p.
Chip Select Module 12.4.1 Chip Select Module Registers The chip select module is programmed through the chip select address registers (CSAR0–CSAR6), chip select mask registers (CSMR0–CSMR6), and the chip select control registers (CSCR0–CSCR6). 12.4.1.1 Chip Select Address Registers (CSAR0–CSAR6) The CSARs, Figure 12-2, specify the chip select base addresses.
Chip Select Module Table 12-7. CSMRn Field Descriptions Bits Name Description 31–16 BAM Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode. 0 Corresponding address bit is used in chip select decode. 1 Corresponding address bit is a don’t care in chip select decode. The block size for CS[6:0] is 2n where n = (number of bits set in respective CSMR[BAM]) + 16.
Chip Select Module 15 14 13 10 9 Field — WS — Reset: CSCR0 — 11_11 — Reset: Other CSCRs 7 6 5 4 3 2 AA PS1 PS0 BEM BSTR BSTW 1 D19 D18 — 0 — — Uninitialized R/W Address 8 R/W 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3); 0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6) Figure 12-4. Chip Select Control Registers (CSCRn) Table 12-8 describes CSCRn fields. Table 12-8.
Chip Select Module Table 12-8. CSCRn Field Descriptions (continued) Bits 3 2–0 Name Description BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn. 0 Break data larger than the specified port size into individual port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
Chip Select Module MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 13 External Interface Module (EIM) This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 15, “Synchronous DRAM Controller Module,” describes DRAM cycles. NOTE Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 13.
External Interface Module (EIM) 13.3 Bus Characteristics The device uses its system clock to generate CLKOUT. Therefore, the external bus operates at the same speed as the bus clock rate, where all bus operations are synchronous to the rising edge of CLKOUT, and some of the bus control signals (BS, OE, and CSn,) are synchronous to the falling edge, shown in Figure 13-1. Bus characteristics may differ somewhat for interfacing with external DRAM.
External Interface Module (EIM) Byte Enable BS3 BS2 BS1 BS0 D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 Processor External Data Bus 8-Bit Port Memory Driven with indeterminate values Byte 0 Byte 1 Byte 2 Driven with indeterminate values Byte 3 Figure 13-2.
External Interface Module (EIM) Table 13-2. Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSCR Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Basic operation of the bus is a three-clock bus cycle: 1. During the first clock, the address, attributes, and TS are driven. 2.
External Interface Module (EIM) Next Cycle S0 S5 S1 Basic Read/Write Fast Termination S4 S2 Wait States S3 Figure 13-4. Data Transfer State Transition Diagram Table 13-3 describes the states as they appear in subsequent timing diagrams. Table 13-3. Bus Cycle States State Cycle CLKOUT Description S0 All High The read or write cycle is initiated in S0.
External Interface Module (EIM) Table 13-3. Bus Cycle States (continued) State S5 Cycle S5 CLKOUT Low Description CS, BS, and OE are negated on the CLKOUT falling edge of S5. The processor stops driving address lines and R/W on the rising edge of CLKOUT, terminating the read or write cycle. At the same time, the processor negates TIP, and SIZ[1:0] on the rising edge of CLKOUT. Note that the rising edge of CLKOUT may be the start of S0 for the next access cycle.
External Interface Module (EIM) S0 S1 S2 S3 S4 S5 CLKOUT R/W A[31:0], SIZ[1:0] TIP TS CSn, BSn, OE Read D[31:0] TA Figure 13-6. Basic Read Bus Cycle Note the following characteristics of a basic read: • In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted. • In S4, the external device can stop driving data after the rising edge of CLKOUT. However data could be driven up to S5.
External Interface Module (EIM) The write cycle timing diagram is shown in Figure 13-8. S0 S1 S2 S3 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn Write D[31:0] TA Figure 13-8. Basic Write Bus Cycle Table 13-3 describes the six states of a basic write cycle. 13.4.5 Fast Termination Cycles Two clock cycle transfers are supported on the external bus.
External Interface Module (EIM) S0 S1 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn D[31:0] Write TA Figure 13-10. Write Cycle with Fast Termination 13.4.6 Back-to-Back Bus Cycles The processor runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle.
External Interface Module (EIM) 13.4.7 Burst Cycles The processor can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst cycle. A line transfer to a 32-bit port would take a 4-longword burst cycle. The external bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize DMA transfers. A user can add wait states by delaying termination of the cycle.
External Interface Module (EIM) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE Read Read D[31:0] Read Read TA Figure 13-12. Line Read Burst (2-1-1-1), External Termination Figure 13-13 shows timing when internal termination is used. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 CLKOUT A[31:0] A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE D[31:0] Read Read Read Read TA Figure 13-13.
External Interface Module (EIM) . WS S0 S1 S2 S3 S4 S5 WS S6 S7 WS S8 S9 WS S10 S12 S13 S11 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE Read D[31:0] Read Read Read TA Figure 13-14. Line Read Burst (3-2-2-2), External Termination Figure 13-15 shows a burst-inhibited line read access with fast termination. The external device executes a basic read cycle while determining that a line is being transferred. The external device uses fast termination for subsequent transfers.
External Interface Module (EIM) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 CLKOUT A[31:0] Internal Termination A[31:0] External Termination SIZ[1:0] R/W, TIP TS CSn, OE, BSn Write D[31:0] Write Write Write TA Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination Figure 13-17 shows a line burst write with one wait-state insertion.
External Interface Module (EIM) S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 CLKOUT A[31:0] A[3:2] = 00 A[3:2] = 01 R/W, TIP SIZ[1:0] Line Longword TS CSn OE, BSn D[31:0] Write Write Write Write TA Basic Fast Fast Fast Figure 13-18. Line Write Burst-Inhibited 13.5 Misaligned Operands Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be misaligned.
External Interface Module (EIM) 31 24 23 16 15 87 0 A[2:0] Transfer 1 — — — Byte 0 001 Transfer 2 Byte 1 — — — 100 Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
External Interface Module (EIM) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 14 Signal Descriptions This chapter describes the processor’s external signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used. Chapter 13, “External Interface Module (EIM),” describes how these signals interact. NOTE The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals.
Signal Descriptions RCON Reset Controller RSTO JTAG Port TDI/DSI TRST/DSCLK TEA 4 JTAG_EN TEST RSTI TCLK TMS/BKPT PST[3:0] CLKMOD1 TDO/DSO Power Management Chip Configuration CLKMOD0 TA TS BS[3:0] 4 OE SIZ[1:0] 2 External Interface Module Test Controller Debug Module Ports Module DDATA[3:0] 4 ColdFire V2 Core R/W Flash Module VDDF TIP 64K SRAM 32 Note: Not present on MCF5280 24 DIV D[31:0] VSTBY EMAC A[23:0] 2-Kbyte D-Cache/I-Cache Edgeport IRQ[7:1] Interrupt Cont
Signal Descriptions Table 14-1 lists the external signals grouped by functionality. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 14-1. MCF5282 Signal Description Signal Name Abbreviation Function I/O Page External Memory Interface Address A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. I/O 14-19 Data D[31:0] Data bus.
Signal Descriptions Table 14-1. MCF5282 Signal Description (continued) Signal Name Abbreviation Function I/O Page SDRAM write enable DRAMW Asserted to signify that a DRAM write cycle is underway. Negated to indicate a read cycle. O 14-21 SDRAM bank selects SDRAM_CS[1:0] Interface to the chip-select lines of the SDRAMs within a memory block. O 14-21 SDRAM clock enable SCKE SDRAM clock enable. O 14-22 Clock and Reset Signals Reset in RSTI Asserted to enter reset exception processing.
Signal Descriptions Table 14-1. MCF5282 Signal Description (continued) Signal Name Abbreviation Function I/O Page Receive data valid ERXDV Asserted to indicate that the PHY has valid nibbles present on the MII. I 14-24 Receive data 0 ERXD0 Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted). I 14-24 Carrier receive sense ECRS Asserted to indicate that the transmit or receive medium is not idle.
Signal Descriptions Table 14-1. MCF5282 Signal Description (continued) Signal Name Abbreviation Function I/O Page Clear-to-send UCTS[1:0] Signals UART that it can begin data transmission. I 14-26 Request to send URTS[1:0] Automatic UART request to send outputs. O 14-27 General Purpose Timer Signals GPTA GPTA[3:0] Provide the external interface to the timer A functions. I/O 14-27 GPTB GPTB[3:0] Provide the external interface to the timer B functions.
Signal Descriptions Table 14-1. MCF5282 Signal Description (continued) Signal Name Abbreviation Function I/O Page Development serial input/Test data DSI/TDI Provides single-bit communication for debug module commands (DSI). Provides serial data port for loading JTAG boundary scan, bypass, and instruction registers (TDI). I 14-30 Development serial output/Test data DSO/TDO Provides single-bit communication for debug module responses (DSO).
Signal Descriptions Table 14-2. MCF5282 Alphabetical Signal Index Abbreviation Function I/O A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. I/O AN[0:3]/AN[W:Z] Direct analog input ANn, or multiplexed input ANx. AN[52:53]/MA[0:1] Direct analog input ANn, or multiplexed output MAn. MAn selects the output of the external multiplexer. AN[55:56]/ TRIG[1:2] Direct analog input ANn, or input TRIGn. TRIGn causes one of the two queues to execute.
Signal Descriptions Table 14-2. MCF5282 Alphabetical Signal Index (continued) Abbreviation Function I/O EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal. Note: Not available on MCF5214 and MCF5216 O EMDIO Transfers control information between the external PHY and the media access controller. Note: Not available on MCF5214 and MCF5216 I/O ERXCLK Provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
Signal Descriptions Table 14-2. MCF5282 Alphabetical Signal Index (continued) Abbreviation Function I/O JTAG_EN Selects between multiplexed debug module and JTAG signals at reset. I OE Indicates when an external device can drive data on the bus. O VDDPLL Isolate the PLL analog circuitry from digital power supply noise. I VDD Supplies positive power to the core logic and I/O pads. I PST[3:0] Indicate core status.
Signal Descriptions Table 14-2. MCF5282 Alphabetical Signal Index (continued) Abbreviation Function I/O TEST Reserved, should be connected to VSS. I TCK JTAG test logic clock. I TIP Asserted to indicate that a bus transfer is in progress. Negated during idle bus cycles. O TS Asserted during the first CLKOUT cycle of a transfer when address and attributes are valid. O UCTS[1:0] Signals UART that it can begin data transmission. I URTS[1:0] Automatic UART request to send outputs.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-3.
Signal Descriptions Table 14-4. Pin Reset States at Reset (Single-Chip Mode) (continued) Signal Reset I/O Debug Support Signals 14.1.2 JTAG_EN — I DSCLK/TRST — I BKPT/TMS — I DSI/TDI — I DSO/TDO High O TCLK — I DDATA[3:0] DDATA{3:0] O PST[3:0] PST[3:0] O External Boot Mode When booting from external memory, the address bus, data bus, and bus control signals will default to their bus functionalities as shown in Table 14-5.
Signal Descriptions 14.2.1.1 Address Bus (A[23:0]) The 24 dedicated address signals, A[23:0], define the address of external byte, word, longword and 16-byte burst accesses. These three-state outputs are the 24 lsbs of the internal 32-bit address bus. The address lines also serve as the SDRAM addressing, providing multiplexed row and column address signals. These pins are configured for GPIO ports F, G and H in single-chip mode. The A[23:21] pins can also be configured for CS[6:4]. 14.2.1.
Signal Descriptions 14.2.1.6 Transfer Error Acknowledge (TEA) This signal indicates an error condition exists for the bus transfer. The bus cycle is terminated and the CPU begins execution of the access error exception. This signal is an input in master mode. This pin can also be configured as GPIO PE5. 14.2.1.7 Read/Write (R/W) This output signal indicates the direction of the data transfer on the bus. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device.
Signal Descriptions 14.2.1.10 Transfer In Progress (TIP) The TIP output is asserted indicating a bus transfer is in progress. It is negated during idle bus cycles. Note that TIP is held asserted on back-to-back cycles. NOTE TIP is not asserted during SDRAM accesses. This pin can also be configured as GPIO PE0 or SYNCB. 14.2.1.
Signal Descriptions 14.2.2.5 SDRAM Clock Enable (SCKE) This output is the SDRAM clock enable. This pin is configured as GPIO PSD0 in single-chip mode. 14.2.3 Clock and Reset Signals The clock and reset signals configure the device and provide interface signals to the external system. 14.2.3.1 Reset In (RSTI) Asserting RSTI causes the device to enter reset exception processing. When RSTI is recognized the address bus, data bus, SIZ, R/W, AS, and TS are three-stated.
Signal Descriptions 14.2.5 14.2.5.1 External Interrupt Signals External Interrupts (IRQ[7:1]) These inputs are the external interrupt sources. See Chapter 11, “Edge Port Module (EPORT)” for more information on these interrupt sources and their corresponding registers. These pins are configured as GPIO PNQ[7:1] in single-chip mode. 14.2.6 Ethernet Module Signals The following signals are used by the Ethernet module for data and clock signals.
Signal Descriptions 14.2.6.6 Collision (ECOL) The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. This pin can also be configured as GPIO PEH4. 14.2.6.7 Receive Clock (ERXCLK) The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER. This pin can also be configured as GPIO PEH3. 14.2.6.
Signal Descriptions 14.2.6.14 Receive Error (ERXER) ERXER is an input signal which when asserted along with ERXDV signals that the PHY has detected an error in the current frame. When ERXDV is not asserted ERXER has no effect, and applies to MII mode operation. These pins can also be configured as GPIO PEL0. 14.2.7 14.2.7.
Signal Descriptions 14.2.9 I2C Signals The I2C module acts as a two-wire, bidirectional serial interface between the processor and peripherals with an I2C interface (such as LCD controller, A-to-D converter, or D-to-A converter). Devices connected to the I2C must have open-drain or open-collector outputs. 14.2.9.1 Serial Clock (SCL) This bidirectional open-drain signal is the clock signal for the I2C interface.
Signal Descriptions 14.2.10.4 Request-to-Send (URTS[1:0]) The URTS[1:0] signals are automatic request to send outputs from the UART modules. URTS[1:0] can also be configured to be asserted and negated as a function of the Rx FIFO level. The URTS[1:0] outputs are each offered as secondary functions on four pins: DTIN3, DTOUT3, DTIN1 and DTOUT1. 14.2.11 General Purpose Timer Signals These pins provide the external interface to the general purpose timer functions. 14.2.11.
Signal Descriptions This pin can also be configured as GPIO PTD3, secondary function URTS1, or secondary function URTS0. 14.2.12.4 DMA Timer 1 Output (DTOUT1) The programmable DMA timer output (DTOUT1) pulse or toggle on various timer events. This pin can also be configured as GPIO PTD2, secondary function URTS1, or secondary function URTS0. 14.2.12.5 DMA Timer 2 Input (DTIN2) The DMA timer 2 input (DTIN2) can be programmed to cause events to occur in DMA timer 2.
Signal Descriptions 14.2.13.3 QADC Analog Input (AN2/ANY) This PQB signal is the direct analog input AN2. When using external multiplexing this pin can also be configured as multiplexed input ANY. This pin can also be configured as GPIO PQB2. 14.2.13.4 QADC Analog Input (AN3/ANZ) This PQB signal is the direct analog input AN3. When using external multiplexing this pin can also be configured as multiplexed input ANZ. This pin can also be configured as GPIO PQB3. 14.2.13.
Signal Descriptions 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST) Debug mode operation: DSCLK is selected. DSCLK is the development serial clock for the serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN. JTAG mode operation: TRST is selected. TRST asynchronously resets the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose the bypass instruction.
Signal Descriptions 14.2.14.7 Debug Data (DDATA[3:0]) Debug data signals (DDATA[3:0]) display captured processor addresses, data and breakpoint status. These pins can also be configured as GPIO PDD[7:4]. 14.2.14.8 Processor Status Outputs (PST[3:0]) PST[3:0] outputs indicate core status, as shown below in Table 14-7. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. These pins can also be configured as GPIO PDD[3:0]. Table 14-7.
Signal Descriptions 14.2.16 Power and Reference Signals These signals provide system power, ground and references to the device. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 14.2.16.1 QADC Analog Reference (VRH, VRL) These signals serve as the high (VRH) and low (VRL) reference potentials for the analog converter in the QADC. 14.2.16.
Chapter 15 Synchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations.
Synchronous DRAM Controller Module DRAM Controller Module D[31:0] internal Q[31:0] internal Data Generation A[23:0] Address Multiplexing Internal Bus Control Logic and State Machine Memory Block 0 Hit Logic DRAM Address/Control Register 0 (DACR0) DRAM Control Register (DCR) Memory Block 1 Hit Logic DRAM Address/Control Register 1 (DACR1) D[31:0] D[31:0] A[23:0] SCAS SRAS SCKE SDRAM_CS[1:0] DRAMW BS[3:0] Refresh Counter Figure 15-1.
Synchronous DRAM Controller Module 15.2 SDRAM Controller Operation By running synchronously with the system clock, SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical burst rate to the SDRAM. Unlike the MCF5272, this processor does not have an independent SDRAM clock signal. For this processor, the timing of the SDRAM controller is controlled by the CLKOUT signal.
Synchronous DRAM Controller Module 15.2.1 DRAM Controller Signals Table 15-2 describes the behavior of DRAM signals in synchronous mode. Table 15-2. Synchronous DRAM Signal Connections Signal Description SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS. SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM.
Synchronous DRAM Controller Module 15 Field 14 — 13 12 11 NAM COC 10 IS Reset 9 8 0 RTIM RC Uninitialized R/W R/W Addr IPSBAR + 0x040 Figure 15-2. DRAM Control Register (DCR) Table 15-4 describes DCR fields. Table 15-4. DCR Field Descriptions Bits Name 15-14 — 13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing is required, the SDRAM should not multiplex addresses on SDRAM accesses.
Synchronous DRAM Controller Module 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1) The DACRn registers, shown in Figure 15-3, contain the base address compare value and the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in DACRn.
Synchronous DRAM Controller Module Table 15-5. DACRn Field Descriptions (continued) Bit Name 10–8 CBM Description Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. CBM determines the addresses onto which these functions are multiplexed. Note: It is important to set CBM according to the location of the command bit.
Synchronous DRAM Controller Module 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1) The DMRn, Figure 15-4, includes mask bits for the base address and for address attributes. 31 18 17 Field 9 BAM — Reset 8 7 6 5 4 3 2 1 0 WP — C/I AM SC SD UC UD V Uninitialized 0 R/W R/W Addr IPSBAR + 0x04C (DMR0), 0x054 (DMR1) Figure 15-4. DRAM Controller Mask Registers (DMRn) Table 15-6 describes DMRn fields. Table 15-6.
Synchronous DRAM Controller Module 15.2.3 General Synchronous Operation Guidelines To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides SDRAM control signals as well as a multiplexed row address and column address to the SDRAM. 15.2.3.1 Address Multiplexing Table 15-7 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table.
Synchronous DRAM Controller Module Table 15-8. Processor to SDRAM Interface (8-Bit Port, 9-Column Address Lines) Process A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 or Pins Row 17 16 15 14 13 12 11 10 9 Column 0 1 2 3 4 5 6 7 8 SDRAM Pins 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-9.
Synchronous DRAM Controller Module Table 15-13. Processor to SDRAM Interface (16-Bit Port, 8-Column Address Lines) Process A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 or Pins Row 16 15 14 13 12 11 10 9 Column 1 2 3 4 5 6 7 8 SDRAM Pins 17 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-14.
Synchronous DRAM Controller Module Table 15-18. Processor to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) Processo A16 r Pins A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Table 15-19.
Synchronous DRAM Controller Module Table 15-23. Processor to SDRAM Interface (32-Bit Port, 12-Column Address Lines) Processor Pins 15.2.3.2 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 SDRAM Byte Strobe Connections Figure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits.
Synchronous DRAM Controller Module Note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the DRAM controller. Thus, instead of the SDRAM enabling its internal burst incrementing capability, the processor controls this function. This means that the burst function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the processor. Figure 15-6 shows a burst read operation.
Synchronous DRAM Controller Module CLKOUT A[23:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL DRAMW D[31:0] SDRAM_CS[0] or [1] BS[3:0] ACTV NOP WRITE WRITE WRITE WRITE NOP PALL Figure 15-7. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. ACTV command 2. NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands). 3.
Synchronous DRAM Controller Module Figure 15-8 shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active. The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits. The REF command is then generated and the delay required by DCR[RTIM] is inserted before the next ACTV command is generated. In this example, the next bus cycle is initiated, but does not generate an SDRAM access until TRC is finished.
Synchronous DRAM Controller Module CLKOUT SRAS SCAS tRCD = 2 tRC = 6 DRAMW SDRAM_CS[0] or [1] SCKE (DCR[COC] = 0) PALL SELF SELFX SelfRefresh Active First Possible ACTV Figure 15-9. Self-Refresh Operation 15.2.4 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this sequence with the following procedure: 1. SDRAM control signals are reset to idle state.
Synchronous DRAM Controller Module 15.2.4.1 Mode Register Settings It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency, through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3. Although the DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs.
Synchronous DRAM Controller Module Table 15-25. SDRAM Example Specifications Parameter Speed grade (-8E) Specification 40 MHz (25-ns period) 10 rows, 8 columns Two bank-select lines to access four internal banks ACTV-to-read/write delay (tRCD) Period between auto-refresh and ACTV command (tRC) ACTV command to precharge command (tRAS) 20 ns (min.) 70 ns 48 ns (min.) Precharge command to ACTV command (tRP) 20 ns (min.
Synchronous DRAM Controller Module 15.3.1 SDRAM Interface Configuration To interface this component to the DRAM controller, use the connection table that corresponds to a 32-bit port size with 8 columns (Table 15-24). Two pins select one of four banks when the part is functional. Table 15-26 shows the proper hardware connections. Table 15-26.
Synchronous DRAM Controller Module Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte Bank 2 512 Kbyte 1 Mbyte Bank 3 512 Kbyte 1 Mbyte 1 Mbyte 512 Kbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 15-12. SDRAM Configuration The DACRs should be programmed as shown in Figure 15-13.
Synchronous DRAM Controller Module Table 15-28. DACR Initialization Values (continued) 15.3.4 Bits Name Setting 3 IP 0 2–0 — Description Indicates precharge has not been initiated. Reserved. Don’t care. DMR Initialization Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition, the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration.
Synchronous DRAM Controller Module 15.3.5 Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding processor address pins must be determined while being aware of masking requirements. Table 15-30 lists the desired initialization setting: Table 15-30.
Synchronous DRAM Controller Module Power-Up Sequence: move.w move.w move.l move.l move.l move.l #0x0026, d0//Initialize DCR d0, DCR #0xFF880300, d0 //Initialize DACR0 d0, DACR0 #0x00740075, d0//Initialize DMR0 d0, DMR0 Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0//Set DACR0[IP] d0, DACR0 #0xBEADDEED, d0//Write and value to memory location to init. precharge d0, 0xFF880000 Refresh Sequence: move.l move.
Chapter 16 DMA Controller Module This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. NOTE The designation “n” is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0, DMA1, DMA2 or DMA3. 16.
DMA Controller Module NOTE Throughout this chapter “external request” and DREQ are used to refer to a DMA request from one of the on-chip UARTS or DMA timers. For details on the connections associated with DMA request inputs, see Section 16.2, “DMA Request Control (DMAREQC).” 16.1.
DMA Controller Module Table 16-1. DMAREQC Field Description (continued) 31–16 — 15–0 DMACn Reserved. Should be cleared. DMA Channel n. Each four bit field defines the logical connection between the DMA requestors and that DMA channel. There are seven possible requesters (4 DMA Timers and 3 UARTs). Any request can be routed to any of the DMA channels. Effectively, the DMAREQC provides a software-controlled routing matrix of the 7 DMA request signals to the 4 channels of the DMA module.
DMA Controller Module 16.3 DMA Transfer Overview The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers to a fast method of moving data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels.
DMA Controller Module Table 16-2. Memory Map for DMA Controller Module Registers DMA IPSBAR Channel Offset 0 Destination address register 0 (DAR0) [p. 16-6] 0x108 DMA control register 0 (DCR0) [p. 16-7] Byte count register 0 (BCR24BIT = 0) 1 Reserved 0x10C Reserved Byte count register 0 (BCR24BIT = 1) 1 (BCR0) [p. 16-7] 0x110 DMA status register 0 (DSR0) [p. 16-10] Reserved 0x140 Source address register 1 (SAR1) [p. 16-5] 0x144 Destination address register 1 (DAR1) [p.
DMA Controller Module 31 0 Field SAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x100, 0x140, 0x180, 0x1C0 Figure 16-4. Source Address Registers (SARn) NOTE The backdoor enable bit must be set in both the core and SCM in order to enable backdoor accesses from the DMA to SRAM. See Section 8.4.2, “Memory Base Address Register (RAMBAR)” for more details.
DMA Controller Module 16.4.3 Byte Count Registers (BCR0–BCR3) BCRn, shown in Figure 16-6 and Figure 16-7, hold the number of bytes yet to be transferred for a given block. The offset within the memory map is based on the value of MPARK[BCR24BIT]. BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively. Figure 16-6 shows BCRn for BCR24BIT = 1.
DMA Controller Module 31 30 Field INT EEXT 29 28 CS AA Reset 27 25 BWC 23 22 — — SINC 21 20 SSIZE 19 DINC 18 17 DSIZE 16 START 0000_0000_0000_0000 R/W R/W 15 Field AT Reset 24 14 0 1 — N/A 0 R/W R/W Address IPSBAR + 0x108, 0x148, 0x188, 0x1C8 Figure 16-8. DMA Control Registers (DCRn) 1 Available only if BCR24BIT = 1, otherwise reserved. Table 16-3 describes DCRn fields. Table 16-3.
DMA Controller Module Table 16-3. DCRn Field Descriptions (continued) Bits Name Description 27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001 (512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of 0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200.
DMA Controller Module Table 16-3. DCRn Field Descriptions (continued) Bits Name Description 15 AT AT is available only if MPARK[BCR24BIT] = 1. DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 Final transfer (when BCR reaches zero).
DMA Controller Module Table 16-4. DSRn Field Descriptions (continued) Bits Name 1 BSY 0 DONE 16.5 Description Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1 BSY is set the first time the channel is enabled after a transfer is initiated. Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully.
DMA Controller Module 16.5.2 Data Transfer Modes Each channel supports dual-address transfers, described in the next section. 16.5.2.1 Dual-Address Transfers Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSRn[REQ] is set. • Dual-address read—The DMA controller drives the SARn value onto the internal address bus.
DMA Controller Module peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address. The DARn should contain the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, the DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register.
DMA Controller Module If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 16.5.4.2 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates.
Chapter 17 Fast Ethernet Controller (FEC) 17.1 Introduction This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. NOTE The MCF5214 and MCF5216 do NOT contain an FEC module. 17.1.
Fast Ethernet Controller (FEC) Internal Bus Crossbar Switch Master Bus Internal Bus Interface MIB Counter RAM Bus Controller Control/Status Registers FIFO RAM FEC DMA FIFO Controller RAM Interface Descriptor Controller (RISC + microcode) FEC Bus MII MDO MDEN Transmit Receive MDI I/O PAD FEC_MDIO FEC_MDC FEC_TXEN FEC_TXD[3:0] FEC_TXER FEC_TXCLK FEC_CRS FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD[3:0] FEC_RXER MII/7-Wire data option Figure 17-1.
Fast Ethernet Controller (FEC) You control the FEC by writing into control registers located in each block. The CSR (control and status registers) block provides global control (Ethernet reset and enable) and interrupt managing registers. The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and FEC_MDIO (management data input/output) lines of the MII interface.
Fast Ethernet Controller (FEC) 17.2 Modes of Operation The primary operational modes are described in this section. 17.2.1 Full and Half Duplex Operation Full duplex mode is for use on point-to-point links between switches or end node to switch. Half duplex mode works in connections between an end node and a repeater or between repeaters. TCR[FDEN] controls duplex mode selection. When configured for full duplex mode, flow control may be enabled.
Fast Ethernet Controller (FEC) 17.3 External Signal Description Table 17-1 describes the various FEC signals, as well as indicating which signals work in available modes. Signal Name MII 7-wire Table 17-1. FEC Signal Descriptions FEC_COL X X FEC_CRS X — When asserted, indicates that transmit or receive medium is not idle. FEC_MDC X — Output clock which provides a timing reference to the PHY for data transfers on the FEC_MDIO signal.
Fast Ethernet Controller (FEC) • • Control/status registers Event/statistic counters held in the MIB block Table 17-2 defines the top level memory map. Table 17-2. Module Memory Map Address Function IPSBAR + 0x1000 – 11FF Control/Status Registers IPSBAR + 0x1200 – 12FF MIB Block Counters Table 17-3 shows the FEC register memory map. Table 17-3.
Fast Ethernet Controller (FEC) 17.4.1 MIB Block Counters Memory Map The MIB counters memory map (Table 17-4) defines the locations in the MIB RAM space where hardware-maintained counters reside.
Fast Ethernet Controller (FEC) Table 17-4.
Fast Ethernet Controller (FEC) Table 17-4. MIB Counters Memory Map (continued) IPSBAR Offset 17.4.2 Register 0x12DC Flow control pause frames received (IEEE_R_FDXFC) 0x12E0 Octet count for frames received without error (IEEE_R_OCTETS_OK) Ethernet Interrupt Event Register (EIR) When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect.
Fast Ethernet Controller (FEC) Table 17-5. EIR Field Descriptions Field Description 31 Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window HBERR following a transmission. 30 BABR Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes. 29 BABT Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes.
Fast Ethernet Controller (FEC) IPSBAR 0x1008 Offset: 31 Access: User read/write 30 29 28 R 27 HB BABR BABT GRA ERR W Reset R 26 25 24 23 22 LC RL UN 0 0 0 TXF TXB RXF RXB MII EB ERR 0 0 0 0 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 17-3. Ethernet Interrupt Mask Register (EIMR) Table 17-6.
Fast Ethernet Controller (FEC) Table 17-7. RDAR Field Descriptions Field Description 31–25 Reserved, must be cleared. 24 RDAR Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, must be cleared. 17.4.
Fast Ethernet Controller (FEC) IPSBAR 0x1024 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER RESET _EN W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-6. Ethernet Control Register (ECR) Table 17-9. ECR Field Descriptions Field Description 31–2 Reserved, must be cleared.
Fast Ethernet Controller (FEC) Table 17-10. MMFR Field Descriptions Field Description 31–30 ST Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame. 29–28 OP Operation code. 00 Write frame operation, but not MII compliant. 01 Write frame operation for a valid MII management frame. 10 Read frame operation for a valid MII management frame. 11 Read frame operation, but not MII compliant. 27–23 PA PHY address.
Fast Ethernet Controller (FEC) 17.4.8 MII Speed Control Register (MSCR) The MSCR provides control of the MII clock (FEC_MDC pin) frequency and allows a preamble drop on the MII management frame. IPSBAR 0x1044 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_ PRE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 MII_SPEED 1 0 0 0 0 0 0 0 0 0 Figure 17-8.
Fast Ethernet Controller (FEC) Table 17-12. Programming Examples for MSCR (continued) 17.4.9 Internal FEC Clock Frequency MSCR[MII_SPEED] FEC_MDC frequency 50 MHz 0xA 2.50 MHz 66 MHz 0xE 2.36 MHz MIB Control Register (MIBC) The MIBC is a read/write register controlling and observing the state of the MIB block. User software accesses this register if there is a need to disable the MIB block operation. For example, to clear all MIB counters in RAM: 1. Disable the MIB block 2.
Fast Ethernet Controller (FEC) IPSBAR 0x1084 Offset: Access: User read/write 31 30 29 28 27 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 26 25 24 23 22 R 0 1 1 19 18 17 16 1 1 0 1 1 1 0 7 6 5 4 3 2 1 0 0 0 W Reset 20 MAX_FL W Reset 21 FCE 0 BC_ MII_ PROM DRT LOOP REJ MODE 0 0 0 0 1 Figure 17-10. Receive Control Register (RCR) Table 17-14.
Fast Ethernet Controller (FEC) IPSBAR 0x10C4 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W 8 7 6 5 4 3 2 1 0 RFC_ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAUSE TFC_ FDEN HBC GTS PAUSE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-11. Transmit Control Register (TCR) Table 17-15. TCR Field Descriptions Field 31–5 Description Reserved, must be cleared. 4 Receive frame control pause.
Fast Ethernet Controller (FEC) IPSBAR 0x10E4 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 PADDR1 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-12. Physical Address Lower Register (PALR) Table 17-16.
Fast Ethernet Controller (FEC) IPSBAR 0x10EC Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R OPCODE 8 7 6 5 4 3 2 1 0 PAUSE_DUR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — — Figure 17-14. Opcode/Pause Duration Register (OPD) Table 17-18. OPD Field Descriptions Field Description 31–16 OPCODE Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.
Fast Ethernet Controller (FEC) IPSBAR 0x111C Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 IADDR2 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-16. Descriptor Individual Lower Address Register (IALR) Table 17-20.
Fast Ethernet Controller (FEC) Table 17-22. GALR Field Descriptions Field Description 31–0 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for GADDR2 receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. 17.4.19 Transmit FIFO Watermark Register (TFWR) The TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can begin.
Fast Ethernet Controller (FEC) Table 17-24. FRBR Field Descriptions Field Description 31–10 Reserved, read as 0 (except bit 10, which is read as 1). 9–2 Read-only. Highest valid FIFO RAM address. R_BOUND 1–0 Reserved, read as 0. 17.4.21 FIFO Receive Start Register (FRSR) FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs.
Fast Ethernet Controller (FEC) IPSBAR 0x1180 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 R_DES_START W 1 0 0 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-22. Ethernet Receive Descriptor Ring Start Register (ERDSR) Table 17-26. ERDSR Field Descriptions Field Description 31–2 Pointer to start of receive buffer descriptor queue. R_DES_START 1–0 Reserved, must be cleared. 17.4.
Fast Ethernet Controller (FEC) To minimize bus utilization (descriptor fetches), it is recommended that EMRBR be greater than or equal to 256 bytes. The EMRBR register is undefined at reset and must be initialized by the user.
Fast Ethernet Controller (FEC) Software produces buffers by allocating/initializing memory and initializing buffer descriptors. Setting the RxBD[E] or TxBD[R] bit produces the buffer. Software writing to TDAR or RDAR tells the FEC that a buffer is placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and consumes the buffers after they have been produced.
Fast Ethernet Controller (FEC) 17.5.1.1.2 Driver/DMA Operation with Receive BDs Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore, the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register. The driver (RxBD software producer) should set up some number of empty buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs.
Fast Ethernet Controller (FEC) Table 17-29. Receive Buffer Descriptor Field Definitions Word Field Description Offset + 0 15 E Empty. Written by the FEC (=0) and user (=1). 0 The data buffer associated with this BD is filled with received data, or data reception has aborted due to an error condition. The status and length fields have been updated as required. 1 The data buffer associated with this BD is empty, or reception is currently in progress.
Fast Ethernet Controller (FEC) Table 17-29. Receive Buffer Descriptor Field Definitions (continued) 1 Word Field Description 0ffset + 4 15–0 A[31:16] RX data buffer pointer, bits [31:16]1 Offset + 6 15–0 A[15:0] RX data buffer pointer, bits [15:0] The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value.
Fast Ethernet Controller (FEC) Table 17-30. Transmit Buffer Descriptor Field Definitions (continued) 1 Word Field Description Offset + 0 13 W Offset + 0 12 TO2 Offset + 0 11 L Last in frame. Written by user. 0 The buffer is not the last in the transmit frame 1 The buffer is the last in the transmit frame Offset + 0 10 TC Transmit CRC. Written by user (only valid if L is set).
Fast Ethernet Controller (FEC) Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the TCR and RCR are not reset, but the entire data path is reset. Table 17-31. ECR[ETHER_EN] De-Assertion Effect on FEC 17.5.
Fast Ethernet Controller (FEC) Table 17-33. FEC User Initialization (Before ECR[ETHER_EN]) (continued) Description Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 17.5.4 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, hardware is ready for operation. Table 17-34 shows microcontroller initialization operations.
Fast Ethernet Controller (FEC) Table 17-35. MII Mode (continued) Signal Description EMAC pin Collision FEC_COL Carrier Sense FEC_CRS Receive Clock FEC_RXCLK Receive Data Valid FEC_RXDV Receive Data FEC_RXD[3:0] Receive Error FEC_RXER Management Data Clock FEC_MDC Management Data Input/Output FEC_MDIO The 7-wire serial mode interface (RCR[MII_MODE] cleared) is generally referred to as AMD mode. Table 17-36 shows the 7-wire mode connections to the external transceiver. Table 17-36.
Fast Ethernet Controller (FEC) If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary.
Fast Ethernet Controller (FEC) 17.5.8 FEC Frame Reception The FEC receiver works with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking. The Ethernet controller receives serial data lsb first. When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately starts processing receive frames. When FEC_RXDV is asserted, the receiver first checks for a valid PA/SFD header.
Fast Ethernet Controller (FEC) group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames appears in the figures below. Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown in Figure 17-27 illustrates the address recognition decisions made by the receive block, while Figure 17-28 illustrates the decisions made by the microcontroller.
Fast Ethernet Controller (FEC) Accept/Reject Frame True Broadcast Addr ? False Receive Address Recognition False Receive Frame Set BC bit in RCV BD True Hash Match ? BC_REJ = 1 ? False True Receive Frame Set MC bit in RCV BD if multicast Exact Match ? True False True Pause Frame ? False Reject Frame Flush from FIFO Notes: BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid PAUSE frame received PROM = 1 ? True Receive Frame
Fast Ethernet Controller (FEC) Receive Address Recognition Group False Individual False True FCE ? False I/G Address ? Pause Address ? Exact Match ? True Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table Match ? True False Receive Frame Reject Frame Flush from FIFO True True Match ? False Receive Frame Reject Frame Notes: Flush from FIFO FCE - field in RCR register (flow control enable) I/G - Individual/Group bit in destination address (lsb in first byte
Fast Ethernet Controller (FEC) The user must initialize the hash table registers. Use this CRC32 polynomial to compute the hash: X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 Eqn. 17-2 Table 17-37 contains example destination addresses and corresponding hash values. Table 17-37.
Fast Ethernet Controller (FEC) Table 17-37.
Fast Ethernet Controller (FEC) Table 17-37. Destination Address to 6-Bit Hash (continued) 48-bit DA 6-bit Hash (in hex) Hash Decimal Value FDFF_FFFF_FFFF 0x3C 60 DDFF_FFFF_FFFF 0x3D 61 9DFF_FFFF_FFFF 0x3E 62 BDFF_FFFF_FFFF 0x3F 63 17.5.11 Full Duplex Flow Control Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
Fast Ethernet Controller (FEC) When the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_PAUSE] may remain set and cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt is not asserted. 17.5.12 Inter-Packet Gap (IPG) Time The minimum inter-packet gap time for back-to-back transmission is 96 bit times.
Fast Ethernet Controller (FEC) 17.5.15.1 Transmission Errors 17.5.15.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed, and EIR[UN] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The UN interrupt is asserted if enabled in the EIMR register. 17.5.15.1.
Fast Ethernet Controller (FEC) 17.5.15.2.3 CRC Error When a CRC error occurs with no dribble bits, FEC closes the buffer and sets RxBD[CR]. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. 17.5.15.2.4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBD[LG] is set. The frame is not truncated unless the frame length exceeds 2047 bytes. 17.5.15.2.
Chapter 18 Watchdog Timer Module 18.1 Introduction The watchdog timer is a 16-bit timer used to help software recover from runaway code. The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown by servicing the watchdog. 18.2 Low-Power Mode Operation This subsection describes the operation of the watchdog module in low-power modes and halted mode of operation.
Watchdog Timer Module 18.3 Block Diagram IPBUS 16-bit WCNTR System Clock 16-bit WSR Count = 0 Divide by 8192 16-bit Watchdog Counter EN Reset Load Counter WAIT DOZE 16-bit WMR HALTED IPBUS Figure 18-1. Watchdog Timer Block Diagram 18.4 Signals The watchdog timer module has no off-chip signals. 18.5 Memory Map and Registers This subsection describes the memory map and registers for the watchdog timer. The watchdog timer has a IPSBAR offset for base address of 0x0014_0000. 18.5.
Watchdog Timer Module Table 18-2. Watchdog Timer Module Memory Map IPSBAR Offset 1 18.5.2 Bits 15–8 Access1 Bits 7–0 0x0014_0000 Watchdog Control Register (WCR) S 0x0014_0002 Watchdog Modulus Register (WMR) S 0x0014_0004 Watchdog Count Register (WCNTR) S/U 0x0014_0006 Watchdog Service Register (WSR) S/U S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access.
Watchdog Timer Module Table 18-3. WCR Field Descriptions Bit(s) Name 15–4 — 3 WAIT Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT. 1 Watchdog timer stopped in wait mode 0 Watchdog timer not affected in wait mode 2 DOZE Doze mode bit. Controls the function of the watchdog timer in doze mode. Once written, the DOZE bit is not affected by further writes except in halted mode.
Watchdog Timer Module Table 18-4. WMR Field Descriptions Bit(s) Name Description 15–0 WM Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a service sequence. Once written, the WM[15:0] field is not affected by further writes except in halted mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads. Reading WMR returns the value in the modulus register.
Watchdog Timer Module Field 15 14 13 12 11 10 9 8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 Reset 0000_0000 R/W Field Reset R/W Address R/W 7 6 5 4 3 2 1 0 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 0000_0000 R/W IPSBAR + 0x0014_0006, 0x0014_0007 Figure 18-5. Watchdog Service Register (WSR) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 19 Programmable Interrupt Timers (PIT0–PIT3) 19.1 Introduction This chapter describes the operation of the four programmable interrupt timer modules: PIT0–PIT3. 19.1.1 Overview Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can count down from the value written in the modulus register or it can be a free-running down-counter. 19.1.
Programmable Interrupt Timers (PIT0–PIT3) NOTE The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. Table 19-1. PIT Module Operation in Low-power Modes Low-power Mode PIT Operation Wait Normal Doze Mode Exit N/A Normal if PCSRn[DOZE] cleared, Any interrupt at or above level in LPICR, exit doze stopped otherwise mode if PCSRn[DOZE] is set.
Programmable Interrupt Timers (PIT0–PIT3) Table 19-2. Programmable Interrupt Timer Modules Memory Map (continued) IPSBAR Offset PIT 0 PIT 1 PIT 2 PIT 3 Width Access1 (bits) Register Reset Value Section/Page 0xFFFF 19.2.3/19-5 User/Supervisor Access Registers 0x15_0004 0x16_0004 0x17_0004 0x18_0004 1 2 PIT Count Register (PCNTRn) 16 R Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
Programmable Interrupt Timers (PIT0–PIT3) Table 19-3. PCSRn Field Descriptions Field Description 15–12 Reserved, must be cleared. 11–8 PRE Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter.
Programmable Interrupt Timers (PIT0–PIT3) Table 19-3. PCSRn Field Descriptions (continued) Field Description 1 RLD Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches 0x0000. 0 Counter rolls over to 0xFFFF on count of 0x0000 1 Counter reloaded from PMRn on count of 0x0000 0 EN PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This bit is read anytime, write anytime.
Programmable Interrupt Timers (PIT0–PIT3) IPSBAR 0x15_0004 (PCNTR0) Offset: 0x16_0004 (PCNTR1) 0x17_0004 (PCNTR2) 0x18_0004 (PCNTR3) 15 14 13 Access: User read only 12 11 10 9 8 R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 PC W Reset 1 1 1 1 1 1 1 1 Figure 19-4. PIT Count Register (PCNTRn) Table 19-5. PCNTRn Field Descriptions Field Description 15–0 PC Counter value. Reading this field with two 8-bit reads is not guaranteed coherent.
Programmable Interrupt Timers (PIT0–PIT3) When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. PIT CLOCK COUNTER 0x0002 0x0001 MODULUS 0x0000 0xFFFF 0x0005 PIF Figure 19-6. Counter in Free-Running Mode 19.3.3 Timeout Specifications The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal bus clock period as selected by the PCSRn[PRE] bits.
Programmable Interrupt Timers (PIT0–PIT3) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 20 General Purpose Timer Modules (GPTA and GPTB) The processor has two 4-channel general purpose timer modules (GPTA and GPTB). Each consists of a 16-bit counter driven by a 7-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
General Purpose Timer Modules (GPTA and GPTB) 20.2 Block Diagram CLK[1:0] System Clock SYNCx Pin PR[2:0] PACLK PACLK/256 PACLK/65536 Divide by 2 MUX Channel 3 Output Compare X Prescaler TCRE CxI GPTCNTH:GPTCNTL CxF Clear Counter 16-Bit Counter TOF Interrupt Request Interrupt Logic TOI TE Channel 0 16-Bit Comparator Edge Detect C0F IOS0 CH. 0 Capture PT0 LOGIC GPTC0H:GPTC0L 16-Bit Latch EDG0A OM:OL0 EDG0B TOV0 CH.
General Purpose Timer Modules (GPTA and GPTB) 20.3 Low-Power Mode Operation This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in the Power Management Module. Table 3-1 shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode. Table 20-1.
General Purpose Timer Modules (GPTA and GPTB) 20.4.3 SYNCn The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter. 20.5 Memory Map and Registers See Table 20-3 for a memory map of the two GPT modules. GPTA has a base address of IPSBAR + 0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000. NOTE Reading reserved or unimplemented locations returns zeroes.
General Purpose Timer Modules (GPTA and GPTB) Table 20-3.
General Purpose Timer Modules (GPTA and GPTB) 20.5.2 GPT Compare Force Register (GPCFORC) 7 Field 4 3 — Reset 0 FOC 0000_0000 R/W R/W Address IPSBAR + 0x1A_00001, 0x1B_0001 Figure 20-3. GPT Input Compare Force Register (GPCFORC) Table 20-5. GPTCFORC Field Descriptions Bit(s) Name 7–4 — 3–0 FOC Description Reserved, should be cleared. Force output compare.Setting an FOC bit causes an immediate output compare on the corresponding channel.
General Purpose Timer Modules (GPTA and GPTB) Table 20-6. GPTOC3M Field Descriptions Bit(s) Name 7–4 — 3–0 OC3M 20.5.4 Description Reserved, should be cleared. Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write anytime.
General Purpose Timer Modules (GPTA and GPTB) Table 20-8. GPTCNT Field Descriptions Bit(s) Name Description 15–0 CNTR Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the prescaler clock.
General Purpose Timer Modules (GPTA and GPTB) Write GPTFLG1 Register Data Bit n CnF Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 20-8. Fast Clear Flag Logic 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV) 7 6 Field 5 4 3 0 — TOV Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_0008, 0x1B_0008 Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV) Table 20-10. GPTTOV Field Descriptions Bit(s) Name 7–4 — 3–0 TOV 20.5.8 Description Reserved, should be cleared.
General Purpose Timer Modules (GPTA and GPTB) Table 20-11. GPTCL1 Field Descriptions Bit(s) Name Description 7–0 OMx/OLx Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each channel. When either OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. These bits are read anytime, write anytime.
General Purpose Timer Modules (GPTA and GPTB) Table 20-13. GPTIE Field Descriptions Bit(s) Name Description 7–4 — Reserved, should be cleared. 3–0 CnI Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled 20.5.
General Purpose Timer Modules (GPTA and GPTB) Table 20-14. GPTSCR2 Field Descriptions (continued) Bit(s) Name Description 2–0 PRn Prescaler bits. Select the prescaler divisor for the GPT counter.
General Purpose Timer Modules (GPTA and GPTB) Table 20-16. GPTFLG2 Field Descriptions Bit(s) Name Description 7 TOF Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect).
General Purpose Timer Modules (GPTA and GPTB) 20.5.15 Pulse Accumulator Control Register (GPTPACTL) Field Reset 7 6 — PAE 5 4 3 PAMOD PEDGE 0 CLK PAOVI PAI 0000_0000 R/W R/W Address IPSBAR + 0x1A_0018, 0x1B_0018 Figure 20-17. Pulse Accumulator Control Register (GPTPACTL) Table 20-18. GPTPACTL Field Descriptions Bit(s) Name Description 7 — 6 PAE 5 PAMOD Pulse accumulator mode. Selects event counter mode or gated time accumulation mode.
General Purpose Timer Modules (GPTA and GPTB) Table 20-18. GPTPACTL Field Descriptions (continued) Bit(s) Name 1 PAOVI 0 PAI Description Pulse accumulator overflow interrupt enable. Enables the PAOVF flag to generate interrupt requests. 1 PAOVF interrupt requests enabled 0 PAOVF interrupt requests disabled Pulse accumulator input interrupt enable. Enables the PAIF flag to generate interrupt requests. 1 PAIF interrupt requests enabled 0 PAIF interrupt requests disabled 20.5.
General Purpose Timer Modules (GPTA and GPTB) 20.5.17 Pulse Accumulator Counter Register (GPTPACNT) 15 0 Field PACNT Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1A_001A, 0x1B_001B Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT) Table 20-20. GPTPACR Field Descriptions Bit(s) Name Description 15–0 PACNT Contains the number of active input edges on the PAI pin since the last reset.
General Purpose Timer Modules (GPTA and GPTB) 20.5.19 GPT Port Data Direction Register (GPTDDR) 7 6 5 4 3 0 Field — DDRT GPT Function — IC/OC Pulse Accumulator Function — PAI Reset — 0000_0000 R/W R/W Address IPSBAR + 0x1A_001E, 0x1B_001E Figure 20-21. GPT Port Data Direction Register (GPTDDR) Table 20-22. GPTDDR Field Descriptions Bit(s) Name 7–4 — 3–0 DDRT 20.6 Description Reserved, should be cleared. Control the port logic of PORTTn.
General Purpose Timer Modules (GPTA and GPTB) 20.6.3 Output Compare Setting an I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the GPT counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets the CnF flag.
General Purpose Timer Modules (GPTA and GPTB) The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE The PA can operate in event counter mode even when the GPT enable bit, GPTEN, is clear. 20.6.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation.
General Purpose Timer Modules (GPTA and GPTB) The PORTTn data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs. To configure a pin for input capture: 1. Clear the pin’s IOS bit in GPTIOS. 2. Clear the pin’s DDR bit in PORTTnDDR. 3. Write to GPTCTL2 to select the input edge to detect. PORTTnDDR does not affect the data direction of an output compare pin.
General Purpose Timer Modules (GPTA and GPTB) Table 20-23. GPT Settings and Pin Functions (continued) 1 2 3 4 5 6 1 0 1 X X 1 Out OC action/ OC3Dn 1 1 1 X X 1 Out OC action/ OC3Dn Output compare Pin readable only if DDR = 06 (ch 3) Output compare/ OC3Dn (ch 3) Pin driven by channel OC action and OC3Dn via channel 3 OC(6) When DDR set the pin as input (0), reading the data register will return the state of the pin.
General Purpose Timer Modules (GPTA and GPTB) NOTE When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures 20.8.2 Pulse Accumulator Overflow (PAOVF) PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in GPTPACTL is also set, PAOVF generates an interrupt request.
General Purpose Timer Modules (GPTA and GPTB) NOTE When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
General Purpose Timer Modules (GPTA and GPTB) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 21 DMA Timers (DTIM0–DTIM3) 21.1 Introduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included.
DMA Timers (DTIM0–DTIM3) Figure 21-1 is a block diagram of one of the four identical timer modules.
DMA Timers (DTIM0–DTIM3) 21.2 Memory Map/Register Definition The timer module registers, shown in Table 21-1, can be modified at any time. Table 21-1. DMA Timer Module Memory Map IPSBAR Offset DMA Timer 0 DMA Timer 1 DMA Timer 2 DMA Timer 3 Width Access (bits) Register Reset Value Section/Page 0x00_0400 0x00_0440 0x00_0480 0x00_04C0 DMA Timer n Mode Register (DTMRn) 16 R/W 0x0000 21.2.1/21-3 0x00_0402 0x00_0442 0x00_0482 0x00_04C2 DMA Timer n Extended Mode Register (DTXMRn) 8 R/W 0x00 21.
DMA Timers (DTIM0–DTIM3) Table 21-2. DTMRn Field Descriptions Field Description 15–8 PS Prescaler value. Divides the clock input (internal bus clock/(16 or 1) or clock on DTINn) 0x00 1 ... 0xFF 256 7–6 CE Capture edge. 00 Disable capture event output. Timer in reference mode. 01 Capture on rising edge only 10 Capture on falling edge only 11 Capture on any edge 5 OM Output mode. 0 Active-low pulse for one internal bus clock cycle (12.5-ns resolution at 80 MHz) 1 Toggle output.
DMA Timers (DTIM0–DTIM3) 21.2.2 DMA Timer Extended Mode Registers (DTXMRn) The DTXMRn registers program DMA request and increment modes for the timers. IPSBAR 0x00_0402 (DTXMR0) Offset: 0x00_0442 (DTXMR1) 0x00_0482 (DTXMR2) 0x00_04C2 (DTXMR3) 7 R Access: User read/write 6 5 4 3 2 1 0 0 0 0 0 0 DMAEN 0 MODE16 W Reset: 0 0 0 0 0 0 0 0 Figure 21-3. DTXMRn Registers Table 21-3. DTXMRn Field Descriptions Field Description 7 DMA request.
DMA Timers (DTIM0–DTIM3) IPSBAR 0x00_0403 (DTER0) Offset: 0x00_0443 (DTER1) 0x00_0483 (DTER2) 0x00_04C3 (DTER3) R Access: User read/write 7 6 5 4 3 2 1 0 0 0 0 0 0 0 REF CAP w1c w1c 0 0 W Reset: 0 0 0 0 0 0 Figure 21-4. DTERn Registers Table 21-4. DTERn Field Descriptions Field Description 7–2 Reserved, must be cleared. 1 REF Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition. Writing a 0 has no effect.
DMA Timers (DTIM0–DTIM3) 21.2.4 DMA Timer Reference Registers (DTRRn) As part of the output-compare function, each DTRRn contains the reference value compared with the respective free-running timer counter (DTCNn). The reference value is matched when DTCNn equals DTRRn. The prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals.
DMA Timers (DTIM0–DTIM3) 21.2.6 DMA Timer Counters (DTCNn) The current value of the 32-bit timer counter can be read at anytime without affecting counting. Writes to DTCNn clear the timer counter. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTINn).
DMA Timers (DTIM0–DTIM3) If the free run/restart bit (DTMRn[FRR]) is set, a new count starts. If it is clear, the timer keeps running. 21.3.4 Output Mode When a timer reaches the reference value selected by DTRR, it can send an output signal on DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output, as selected by the DTMRn[OM] bit. 21.
DMA Timers (DTIM0–DTIM3) *[CE] = 00 *[OM] = 0 *[ORRI] = 0, *[FRR] = 1, *[CLK] = 10, *[RST] = 0, disable capture event output output=active-low pulse disable ref. match output restart mode enabled internal bus clock/16 timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 reference to be move.
DMA Timers (DTIM0–DTIM3) For example, if a 80-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x1312C (78,124 decimal), the time-out period is: 1 Timeout period = -------------------6- × 16 × ( 127 + 1 ) × ( 78124 + 1 ) = 2.00 seconds × 80 10 Eqn. 21-2 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
DMA Timers (DTIM0–DTIM3) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 22 Queued Serial Peripheral Interface (QSPI) 22.1 Introduction This chapter describes the queued serial peripheral interface (QSPI) module. 22.1.1 Block Diagram Figure 22-1 illustrates the QSPI module. Queue Control Block 4 Queue Pointer Comparator End Queue Pointer 80-byte QSPI RAM Done QSPI Address Register QSPI Data Register 4 Control Logic Chip Selects Status Regs msb lsb 8/16 Bit Shift Reg. Logic Array Control Regs QSPI_DIN Rx/Tx Data Reg.
Queued Serial Peripheral Interface (QSPI) 22.1.2 Overview The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.
Queued Serial Peripheral Interface (QSPI) Table 22-1. QSPI Input and Output Signals and Functions Signal Name 22.3 Hi-Z or Actively Driven Function Data output (QSPI_DOUT) Configurable Serial data output from QSPI Data input (QSPI_DIN) N/A Serial data input to QSPI Serial clock (QSPI_CLK) Actively driven Clock output from QSPI Peripheral chip selects (QSPI_CSn) Actively driven Peripheral selects from QSPI Memory Map/Register Definition Table 22-2 is the QSPI register memory map.
Queued Serial Peripheral Interface (QSPI) Table 22-3. QMR Field Descriptions Field 15 MSTR 14 13–10 BITS Description Master mode enable. 0 Reserved, do not use. 1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly. Reserved, must be cleared. Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Queued Serial Peripheral Interface (QSPI) Figure 22-3 shows an example of a QSPI clocking and data transfer. QSPI_CLK QSPI_DOUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb QSPI_DIN 15 A B QSPI_CS QMR[CPOL] = 0 QMR[CPHA] = 1 QCR[CONT] = 0 Chip selects are active low A = QDLYR[QCD] B = QDLYR[DTL] Figure 22-3. QSPI Clocking and Data Transfer Example 22.3.
Queued Serial Peripheral Interface (QSPI) 22.3.3 QSPI Wrap Register (QWR) The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations. IPSBAR 0x00_0348 (QWR) Offset: 15 R W Reset 14 Access: User read/write 13 12 11 10 HALT WREN WRTO CSIV 0 0 0 0 9 8 7 6 ENDQP 0 0 5 4 3 CPTQP 0 0 0 0 2 1 0 NEWQP 0 0 0 0 0 0 Figure 22-5. QSPI Wrap Register (QWR) Table 22-5. QWR Field Descriptions Field Description 15 HALT Halt transfers.
Queued Serial Peripheral Interface (QSPI) Table 22-6. QIR Field Descriptions Field Description 15 Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing WCEFB the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error. 14 ABRTB 13 12 ABRTL Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer.
Queued Serial Peripheral Interface (QSPI) IPSBAR 0x00_0350 (QAR) Offset: R Access: User read/write 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 1 0 0 0 ADDR W Reset 2 0 0 0 0 Figure 22-7. QSPI Address Register (QAR) Table 22-7. QAR Field Descriptions Field Description 15–6 Reserved, must be cleared. 5–0 ADDR 22.3.6 Address used to read/write the QSPI RAM.
Queued Serial Peripheral Interface (QSPI) NOTE The command RAM is accessed only using the most significant byte of QDR and indirect addressing based on QAR[ADDR]. Address: QAR[ADDR] 15 14 Access: CPU write-only 13 12 DT DSCK — — 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 — — — — — — — — R W CONT BITSE Reset — — QSPI_CS — — — — Figure 22-9. Command RAM Registers (QCR0–QCR15) Table 22-9. QCR0–QCR15 Field Descriptions Field Description 15 CONT Continuous.
Queued Serial Peripheral Interface (QSPI) • 32 receive data bytes (receive data RAM) The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF). NOTE Throughout ColdFire documentation, the term word is used to designate a 16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units.
Queued Serial Peripheral Interface (QSPI) 22.4.1 QSPI RAM The QSPI contains an 80-byte block of static RAM that can be accessed by the user and the QSPI. This RAM does not appear in the device memory map, because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
Queued Serial Peripheral Interface (QSPI) the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry. Receive RAM is not writeable. QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. 22.4.1.2 Transmit RAM Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.
Queued Serial Peripheral Interface (QSPI) The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: f sys QMR[BAUD] = ----------------------------------------------------------------------------------2 × [desired QSPI_CLK baud rate] Eqn. 22-1 Table 22-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate Internal Bus Clock = 80 MHz 22.4.3 QMR [BAUD] QSPI_CLK 2 20 MHz 4 10 MHz 8 5 MHz 16 2.5 MHz 32 1.25 Hz 255 156.
Queued Serial Peripheral Interface (QSPI) where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of 8192/fsys. Standard delay period (DT = 0) is calculated by the following: 17 Standard delay after transfer = ------f sys (DT = 0) Eqn. 22-4 Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer.
Queued Serial Peripheral Interface (QSPI) QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE]. There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting QWR[HALT].
Queued Serial Peripheral Interface (QSPI) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 23 UART Modules 23.1 Introduction This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples. NOTE The designation n appears throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0, UART1, or UART2. 23.1.1 Overview The internal bus clock can clock each of the three independent UARTs, eliminating the need for an external UART clock.
UART Modules NOTE The DTINn pin can clock UARTn. However, if the timers are operating and the UART uses DTINn as a clock source, input capture mode is not available for that timer. The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin.
UART Modules • Start/end break interrupt/status 23.2 External Signal Description Table 23-1 briefly describes the UART module signals. Table 23-1. UART Module External Signals Signal Description UTXDn Transmitter Serial Data Output. UTXDn is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on UTXDn on the falling edge of the clock source, with the least significant bit (lsb) sent first. URXDn Receiver Serial Data Input.
UART Modules Table 23-2. UART Module Memory Map UART0 UART1 UART2 Register Width Access Reset Value Section/Page (bit) 0x00 0x0 0x0 UART Mode Registers1 (UMR1n), (UMR2n) 8 R/W 0x00 23.3.1/23-5 23.3.2/23-6 0x04 0x4 0x4 UART Status Register (USRn) 8 R 0x00 23.3.3/23-8 UART Clock Select Register1(UCSRn) 8 W See Section 23.3.4/23-9 0x08 0x8 0x8 UART Command Registers (UCRn) 8 W 0x00 23.3.5/23-9 0x0C 0xC 0xC UART Receive Buffers (URBn) 8 R 0xFF 23.3.
UART Modules 23.3.1 UART Mode Registers 1 (UMR1n) The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
UART Modules Table 23-3. UMR1n Field Descriptions (continued) Field 2 PT Description Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11). 1–0 B/C PM Parity Mode Parity Type (PT= 0) Parity Type (PT= 1) 00 With parity Even parity Odd parity 01 Force parity Low parity High parity 10 No parity 11 Multidrop mode N/A Data character Address character Bits per character.
UART Modules Table 23-4. UMR2n Field Descriptions Field 7–6 CM Description Channel mode. Selects a channel mode. Section 23.4.3, “Looping Modes,” describes individual modes. 00 Normal 01 Automatic echo 10 Local loopback 11 Remote loopback 5 TXRTS Transmitter ready-to-send. Controls negation of URTSn to automatically terminate a message transmission. Attempting to program a receiver and transmitter in the same UART for URTSn control is not permitted and disables URTSn control for both.
UART Modules 23.3.3 UART Status Registers (USRn) The USRn registers show the status of the transmitter, the receiver, and the FIFO. IPSBAR 0x00_0204 (USR0) Offset: 0x00_0244 (USR1) 0x00_0284 (USR2) R Access: User read-only 7 6 5 4 3 2 1 0 RB FE PE OE TXEMP TXRDY FFULL RXRDY 0 0 0 0 0 0 0 0 W Reset: Figure 23-5. UART Status Registers (USRn) Table 23-5. USRn Field Descriptions Field Description 7 RB Received break.
UART Modules Table 23-5. USRn Field Descriptions (continued) Field Description 1 FFULL FIFO full. 0 The FIFO is not full but may hold up to two unread characters. 1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost. 0 RXRDY Receiver ready. 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read. 1 One or more characters were received and are waiting in the receive buffer FIFO. 23.3.
UART Modules IPSBAR 0x00_0208 (UCR0) Offset: 0x00_0248 (UCR1) 0x00_0288 (UCR2) 7 Access: User write-only 6 5 4 3 2 1 0 R W 0 Reset: 0 MISC 0 0 TC 0 0 RC 0 0 0 Figure 23-7. UART Command Registers (UCRn) Table 23-7 describes UCRn fields and commands. Examples in Section 23.4.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. Table 23-7. UCRn Field Descriptions Field 7 6–4 MISC Description Reserved, must be cleared.
UART Modules Table 23-7. UCRn Field Descriptions (continued) Field 3–2 TC Description Transmit command field. Selects a single transmit command. Command 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 TRANSMITTER Enables operation of the UART’s transmitter. USRn[TXEMP,TXRDY] are set. If the transmitter is already enabled, this command has no effect.
UART Modules IPSBAR 0x00_020C (URB0) Offset: 0x00_024C (URB1) 0x00_028C (URB2) 7 6 Access: User read-only 5 4 R 3 2 1 0 1 1 1 1 RB W Reset: 1 1 1 1 Figure 23-8. UART Receive Buffer (URBn) 23.3.7 UART Transmit Buffers (UTBn) The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USRn[TXRDY] is set.
UART Modules Table 23-8. UIPCRn Field Descriptions Field Description 7–5 Reserved 4 COS Change of state (high-to-low or low-to-high transition). 0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS]. 1 A change-of-state longer than 25–50 μs occurred on the UCTSn input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected. 3–1 Reserved 0 CTS Current state of clear-to-send.
UART Modules NOTE True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. IPSBAR 0x00_0214 (UISR0) Offset: 0x00_0254 (UISR1) 0x00_0294 (UISR2) Access: User read/write 7 6 5 4 3 2 1 0 R (UISRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY W (UIMRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY 0 0 0 0 0 0 0 0 Reset: Figure 23-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn) Table 23-10.
UART Modules 23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation, as described in Section 23.4.1.2.1, “Internal Bus Clock Baud Rates.
UART Modules Table 23-11. UIPn Field Descriptions Field Description 7–1 Reserved 0 CTS Current state of clear-to-send. The UCTSn value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as UIPCRn[CTS]. 0 The current state of the UCTSn input is logic 0. 1 The current state of the UCTSn input is logic 1. 23.3.
UART Modules 23.4.1.1 Programmable Divider As Figure 23-17 shows, the UARTn transmitter and receiver can use the following clock sources: • An external clock signal on the DTINn pin. When not divided, DTINn provides a synchronous clock; when divided by 16, it is asynchronous. • The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by the 16-bit value programmed in UBG1n and UBG2n. See Section 23.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).
UART Modules Using a 80-MHz internal bus clock and letting baud rate equal 9600, then 80MHz Divider = ------------------------------- = 260 ( decimal ) = 0x0104 ( hexadecimal ) [ 32 x 9600 ] Eqn. 23-2 Therefore, UBG1n equals 0x01 and UBG2n equals 0x04. 23.4.1.2.2 External Clock An external source clock (DTINn) passes through a divide-by-1 or 16 prescaler. If fextc is the external clock frequency, baud rate can be described with this equation: f extc Baudrate = --------------------(16 or 1) 23.4.
UART Modules optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer (UTBn).
UART Modules C1 in transmission C11 UTXDn C2 C3 C4 Break C6 Transmitter Enabled USRn[TXRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 UCTSn3 URTSn4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TXCTS] = 1 4 UMR2n[TXRTS] = 1 Figure 23-19. Transmitter Timing Diagram 23.4.2.2 Receiver The receiver is enabled through its UCRn, as described in Section 23.3.
UART Modules framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USRn at the received character boundary. They are valid only if USRn[RXRDY] is set. If a break condition is detected (URXDn is low for the entire character including the stop bit), a character of all 0s loads into the receiver holding register and USRn[RB,RXRDY] are set.
UART Modules programming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block modes. USRn[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO.
UART Modules 23.4.3.1 Automatic Echo Mode In automatic echo mode, shown in Figure 23-21, the UART automatically resends received data bit by bit. The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on UTXDn. The receiver must be enabled, but the transmitter need not be. URXDn Input Rx CPU Disabled Tx Disabled UTXDn Output Figure 23-21.
UART Modules Disabled Rx Disabled URXDn Input Disabled UTXDn Output CPU Disabled Tx Figure 23-23. Remote Loopback 23.4.4 Multidrop Mode Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations. Although slave stations have their receivers disabled, they continuously monitor the master’s data stream.
UART Modules Master Station A/D UTXDn ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled USRn[TXRDY] internal module select C0 UMR1n[PM] = 11 ADD 1 UMR1n[PT] = 1 UMR1n[PT] = 0 ADD 2 UMR1n[PT] = 1 Peripheral Station URXDn A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled USRn[RXRDY] internal module select UMR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 23-24.
UART Modules 23.4.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 23.4.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 23.4.5.2 Write Cycles The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers complete normally without an error termination, but data is ignored. 23.
UART Modules 3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts. 4. If TXRDY or RXRDY generates interrupt requests, verify that DMAREQC (in the SCM) does not also assign the UART’s TXRDY and RXRDY into DMA channels. 5. Initialize interrupts in the UART, see Table 23-13. Table 23-13. UART Interrupts 23.5.1.
UART Modules To configure the UART for DMA requests: 1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA channels. For example, setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to DMA channel 1, setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA channel 2, and so on. It is possible to independently map transmit-based and receive-based UART DMA requests in the DMAREQC. 2. Disable interrupts using the UIMR register.
UART Modules 23.5.2 UART Module Initialization Sequence The following shows the UART module initialization sequence. 1. UCRn: a) Reset the receiver and transmitter. b) Reset the mode pointer (MISC[2–0] = 0b001). 2. UIMRn: Enable the desired interrupt sources. 3. UACRn: Initialize the input enable control (IEC bit). 4. UCSRn: Select the receiver and transmitter clock. Use timer as source if required. 5. UMR1n: a) If preferred, program operation of receiver ready-to-send (RXRTS bit).
UART Modules Enable Serial Module Any Errors? Y SINIT N Initiate: Channel Interrupts Enable Receiver CHK1 Assert Request To Send Call CHCHK SINITR Save Channel Status Return Figure 23-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
UART Modules CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK N Is Transmitter Ready? N Waited Too Long? Y Set TransmitterNever-ready Flag Y Set ReceiverNever-ready Flag Y SNDCHR Send Character To Transmitter RxCHK N Has Character Been Received? N Waited Too Long? Y B A Figure 23-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
UART Modules A B RSTCHN FRCHK Have Framing Error? N Disable Transmitter Y Restore To Original Mode Set Framing Error Flag PRCHK Have Parity Error? N Return Y Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Y N Set Incorrect Character Flag B Figure 23-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
UART Modules INCH SIRQ ABRKI Was IRQ Caused By Beginning Of A Break? N Y Does Channel A Receiver Have A Character? N Y Clear Change-inBreak Status Bit Place Character In D0 ABRKI1 Has End-of-break IRQ Arrived Yet? N Return Y Clear Change-inBreak Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR RTE Figure 23-25.
UART Modules OUTCH Is Transmitter Ready? N Y Send Character To Transmitter Return Figure 23-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 24 I2C Interface 24.1 Introduction This chapter describes the I2C module, clock synchronization, and I2C programming model registers. It also provides extensive programming examples. 24.1.1 Block Diagram Figure 24-1 is a I2C module block diagram, illustrating the interaction of the registers described in Section 24.2, “Memory Map/Register Definition”.
I2C Interface 24.1.2 Overview I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications that require occasional communication between many devices over a short distance. The flexible I2C bus allows additional devices to connect to the bus for expansion and system development. The interface operates up to 100 Kbps with maximum bus loading and timing.
I2C Interface 24.2 Memory Map/Register Definition The below table lists the configuration registers used in the I2C interface. Table 24-1. I2C Module Memory Map IPSBAR Offset Register Access Reset Value Section/Page 0x00_0300 I2C Address Register (I2ADR) R/W 0x00 24.2.1/24-3 0x00_0304 I2C Frequency Divider Register (I2FDR) R/W 0x00 24.2.2/24-3 2 0x00_0308 I C Control Register (I2CR) R/W 0x00 24.2.3/24-4 0x00_030C I2C Status Register (I2SR) R/W 0x81 24.2.4/24-5 R/W 0x00 24.2.
I2C Interface IPSBAR 0x00_0304 (I2FDR) Offset: R 7 6 0 0 Access: User read/write 5 4 3 2 1 0 0 0 0 IC W Reset: 0 0 0 0 0 Figure 24-3. I2C Frequency Divider Register (I2FDR) Table 24-3. I2FDR Field Descriptions Field Description 7–6 Reserved, must be cleared. 5–0 IC I2C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below.
I2C Interface IPSBAR 0x00_0308 (I2CR) Offset: Reset: Access: User read/write 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Figure 24-4. I2C Control Register (I2CR) Table 24-4. I2CR Field Descriptions Field Description 7 IEN I2C enable. Controls the software reset of the entire I2C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.
I2C Interface Table 24-5. I2SR Field Descriptions Field 7 ICF 6 IAAS Description I2C Data transferring bit. While one byte of data is transferred, ICF is cleared. 0 Transfer in progress 1 Transfer complete. Set by falling edge of ninth clock of a byte transfer. I2C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit. 0 Not addressed. 1 Addressed as a slave.
I2C Interface IPSBAR 0x00_0310 (I2DR) Offset: 7 Access: User read/write 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset: 0 0 0 0 Figure 24-6. I2C Data I/O Register (I2DR) Table 24-6. I2DR Field Description Field Description 7–0 DATA I2C data. When data is written to this register in master transmit mode, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data.
I2C Interface Interrupt bit set (Byte complete) msb I2C_SCL 2 3 4 5 6 7 msb 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W A Interrupt is serviced lsb 1 I2C_SDA I2C_SCL held low while Calling Address START Signal XXX B 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 C 9 Data Byte ACK Bit R/W lsb 1 No ACK Bit E D STOP Signal F 2 Figure 24-7. I C Standard Communication Protocol 24.3.
I2C Interface 24.3.4 Acknowledge The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in Figure 24-9. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it remains stable low during the high period of the clock pulse. If it does not acknowledge the master, the slave receiver must leave I2C_SDA high.
I2C Interface msb I2C_SCL 1 I2C_SDA lsb 2 3 4 5 6 7 9 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START Signal Calling Address lsb msb 8 XX R/W ACK Bit 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W New Calling Address Repeated START Signal A R/W No ACK Bit STOP Signal Figure 24-10. Repeated START Various combinations of read/write formats are then possible: • The first example in Figure 24-11 is the case of master-transmitter transmitting to slave-receiver.
I2C Interface 24.3.7 Clock Synchronization and Arbitration I2C is a true multi-master bus that allows more than one master connected to it. If two or more master devices simultaneously request control of the bus, a clock synchronization procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line, a high-to-low transition on the I2C_SCL line affects all the devices connected on the bus.
I2C Interface 24.3.8 Handshaking and Clock Stretching The clock synchronization mechanism can acts as a handshake in data transfers. Slave devices can hold I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL. Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can drive I2C_SCL low for the required period and then release it.
I2C Interface processor may need to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions. The following example signals START and transmits the first byte of data (slave address): 1. Check I2SR[IBB]. If it is set, wait until it is clear. 2. After cleared, set to transmit mode by setting I2CR[MTX]. 3. Set master mode by setting I2CR[MSTA]. This generates a START condition. 4. Transmit the calling address via the I2DR. 5. Check I2SR[IBB].
I2C Interface For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example. 1. Decrement RXCNT. 2. If last byte (RXCNT = 0) go to step #4. 3. If next to last byte (RXCNT = 1), set I2CR[TXAK] to disable ACK and go to step #5. 4.
I2C Interface Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? N Last Byte Transmitted ? N RXAK= 0 ? Clear IAL Y Last Byte to be Read ? N Y Y N End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR N Y Y (Read)Y N Data Cycle SRW=1 ? Generate STOP Signal Switch to Rx Mode Generate STOP Signal Tx/Rx ? N (WRITE) N Read Data from I2DR And Store RX TX ACK from Receiver ? N Y Set TX Mode Write Data to I2DR Dummy Read from I2DR IAAS=1 ? Address Y Cycle 2nd La
I2C Interface MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 25 FlexCAN The FlexCAN module is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbit/sec), short distance, priority based protocol which can communicate using a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires).
FlexCAN A block diagram describing the various submodules of the FlexCAN module is shown in Figure 25-1. Each submodule is described in detail in subsequent sections. MB15 MB14 Control MB13 Transmitter CANTX Receiver CANRX MB12 MB # (0-15) 0.25k/0.5KB RAM MB3 MB2 MB1 Bus Interface Unit MB0 Internal Bus Figure 25-1. FlexCAN Block Diagram and Pinout 25.1.
FlexCAN Table 25-1. FlexCAN Memory Map (continued) IPSBAR Offset [31:24] 0x1C_0008 [23:16] [15:8] Prescaler Divider (PRESDIV) Control Register 2 (CANCTRL2) 0x1C_000C Free Running Timer (TIMER) Reserved Reserved 0x1C_0010 Rx Global Mask (RXGMASK) 0x1C_0014 Rx Buffer 14 Mask (RX14MASK) 0x1C_0018 Rx Buffer 15 Mask (RX15MASK) 0x1C_0020 Error and Status (ESTAT) 0x1C_0024 Interrupt Flags (IFLAG) 0x1C_0034– 0x1C_007F Reserved 0x1C_0080– 0x1C_017F 25.1.
FlexCAN 25.2 The CAN System A typical CAN system is shown below in Figure 25-2. CAN Station 2 CAN Station 1 CAN Station n ColdFire Processor FlexCAN CANTX CANRX Transceiver CAN Bus Figure 25-2. Typical CAN system Each CAN station is connected physically to the CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus.
FlexCAN 0x0 15–8 7–4 3–0 TIME STAMP CODE LENGTH 0x2 ID[28:18] 0x4 SRR IDE ID[17-15] ID[14-0] ID_HIGH RTR ID_LOW 0x6 DATA BYTE 0 DATA BYTE 1 0x8 DATA BYTE 2 DATA BYTE 3 0xA DATA BYTE 4 DATA BYTE 5 0xC DATA BYTE 6 DATA BYTE 7 0xE CONTROL/STATUS Reserved Figure 25-3.
FlexCAN Table 25-2. Common Extended/Standard Format Frames Field Description Time Stamp Contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the CAN bus. Code Refer to Table 25-3 and Table 25-4. Rx Length Length (in bytes) of the Rx data stored in offset 0x6 through 0xD of the buffer. This field is written by the FlexCAN module, copied from the data length code (DLC) field of the received frame.
FlexCAN 25.3.1.2 Fields for Extended Format Frames Table 25-5 describes the message buffer fields used only for extended identifier format frames. Table 25-5. Extended Format Frames Field Description ID[28:18]/[17:15] Contains the 14 most significant bits of the extended identifier, located in the ID HIGH word of the message buffer. Substitute Contains a fixed recessive bit, used only in extended format. Should be set to one by the user for Remote Request Tx buffers.
FlexCAN Message Buffers FlexCAN Base Address Offset Control/Status ID_HIGH ID_LOW 0x80-0x8F 0x82 0x84 0x86 Message Buffer 0 8 bytes Data field 0x8C 0x8E Reserved 0x90 Message Buffer 1 0x9E 0xA0 Message Buffer 2 0xAE Message Buffer 3 0xB0 through 0x16E Message Buffer 14 0x170 Message Buffer 15 0x17E Figure 25-5. FlexCAN Memory Map 25.
FlexCAN • • Writing the Data bytes Writing the Control/Status word (active Code, Length) NOTE The first and last steps are mandatory! Starting from the last step, this MB will participate in the internal arbitration process, which takes place every time the CAN bus is sensed as free by the receiver or at the inter-frame space, and there is at least one MB ready for transmission. This internal arbitration process is intended to select the MB from which the next frame is transmitted.
FlexCAN Note that the received identifier field is always stored in the matching MB, thus the contents of the identifier field in a MB may change if the match was due to mask. 25.4.2.1 Self-Received Frames The FlexCAN receives self-transmitted frames if there exists a matching receive MB. 25.4.3 Message Buffer Handling To maintain data coherency and proper FlexCAN operation, the CPU must obey the rules listed in Section 25.4.1, “Transmit Process” and in Section 25.4.2, “Receive Process.
FlexCAN Data should never be written into a receive message buffer. If this is done while a message is being transferred from an SMB, the control/status word will reflect a full or overrun condition, but no interrupt will be requested. 25.4.3.4 Locking and Releasing Message Buffers The lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The following examples demonstrate how the lock/release/busy mechanism will affect FlexCAN operation. 1.
FlexCAN A received remote frame is not stored in a receive message buffer. It is only used to trigger the automatic transmission of a frame in response. The mask registers are not used in remote frame ID matching. All ID bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response transmission. 25.4.5 Overload Frames Overload frame transmissions are not initiated by the FlexCAN unless certain conditions are detected on the CAN bus.
FlexCAN Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock System Clock Freq (Mhz) Can bit-rate (Mhz) Possible S-Clock Freq (Mhz) Possible number of time-quanta/bit Pre-Scaler programed value + 1 48 1 8,12,24 8,12,24 3,2,1 40 1 10,20 10,20 2,1 32 1 8,16 8,16 2,1 48 0.125 1,1.5,2,3 8,12,16,24 24,16,12,8 40 0.125 1,2,2.5 8,16,20 20,10,8 32 0.125 1,2 8,16 16,8 25.4.8.
FlexCAN The FlexCAN responds to any bus state as described in the protocol, e.g. transmit error active or error passive flag, delay its transmission start time (Error Passive) and avoid any influence on the bus when in Bus Off state. The following are the basic rules for FlexCAN bus state transitions: • If the value of TXCTR or RXCTR increases to be greater than or equal to 128, the FCS field in the error status register is updated to reflect it (set Error Passive state).
FlexCAN 5. Negate the HALT bit in the module configuration register a) At this point, the FlexCAN will attempt to synchronize with the CAN bus. NOTE In both the transmit and receive processes, the first action in preparing a message buffer should be to deactivate the buffer by setting its code field to the proper value. This requirement is mandatory to assure data coherency. 25.4.11 Special Operating Modes 25.4.11.
FlexCAN To exit low-power stop mode: • Reset the FlexCAN either by asserting RSTI or by setting the SOFTRST bit CANMCR. • Clear the STOP bit in CANMCR. • The FlexCAN module can optionally exit low-power stop mode via the self-wake mechanism. If the SELFWAKE bit in CANMCR was set at the time the FlexCAN entered stop mode, then upon detection of a recessive to dominant transition on the CAN bus, the FlexCAN clears the STOP bit in CANMCR and its clocks begin running.
FlexCAN 25.4.11.3 Auto-Power Save Mode Auto-power save mode enables normal operation with optimized power savings. Once the auto-power save (APS) bit in CANMCR is set, the FlexCAN looks for a set of conditions in which there is no need for its clocks to be running. If these conditions are met, the FlexCAN stops its clocks, thus saving power. The following conditions will activate auto-power save mode. • No Rx/Tx frame in progress.
FlexCAN 25.5.1 CAN Module Configuration Register (CANMCR) Field 15 14 13 12 11 STOP FRZ — HALT NOTRDY Reset 10 9 WAKEMSK SOFTRST 8 FRZACK 0101_1001 R/W R/W Field 7 6 5 4 SUPV SELFWAKE APS STOPACK Reset 3 0 — 1000_0000 R/W R/W Address IPSBAR + 0x1C_0000 Figure 25-6. CAN Module Configuration Register (CANMCR) Table 25-8 describes the CANMCR fields. Table 25-8. CANMCR Field Descriptions Bits Name Description STOP Low-power stop mode enable.
FlexCAN Table 25-8. CANMCR Field Descriptions (continued) Bits Name Description Soft reset. When this bit is asserted, the FlexCAN resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (CANMCR, CANICR, CANTCR, IMASK, and IFLAG). The configuration registers that control the interface with the CAN bus are not changed (CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not changed.
FlexCAN 25.5.2 FlexCAN Control Register 0 (CANCTRL0) 7 6 Field BOFFMSK 5 ERRMSK 4 3 — Reset 2 1 RXMODE 0 TXMODE 0000_0000 R/W R/W Address IPSBAR + 0x1C_0006 Figure 25-7. FlexCAN Control Register 0 (CANCTRL0) Table 25-9 describes the CANCTRL0 fields. Table 25-9. CANCTRL0 Field Descriptions Bits Name 7 BOFFMSK 6 Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt. ERRMSK 0 Error interrupt disabled. 1 Error interrupt enabled.
FlexCAN 25.5.3 FlexCAN Control Register 1 (CANCTRL1) Field 7 6 5 4 3 SAMP — TSYNC LBUF LOM Reset 2 1 0 PROPSEG 0000_0000 R/W R/W Address IPSBAR + 0x1C_0007 Figure 25-8. FlexCAN Control Register 1 (CANCTRL1) Table 25-11 describes the CANCTRL1 fields. Table 25-11. CANCTRL1 Field Descriptions Bits Name Description 7 SAMP Sampling mode. The SAMP bit determines whether the FlexCAN module will sample each received bit one time or three times to determine its value.
FlexCAN 25.5.4 Prescaler Divide Register (PRESDIV) 7 0 Field PRES_DIV Reset 0000_0000 R/W R/W Address IPSBAR + 0x1C_0008 Figure 25-9. Prescaler Divide Register (PRESDIV) Table 25-12 describes the PRESDIV fields. Table 25-12. PRESDIV Field Descriptions Bits 7–0 Name Description PRES_DIV Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency and the serial clock (S-clock).
FlexCAN Table 25-13. CANCTRL2 Field Descriptions (continued) Bits Name 5–3 PSEG PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer segment 1 1 in the bit time. The valid programmed values are 0 through 7. The length of phase buffer segment 1 is calculated as follows: Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta 2–0 PSEG PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer segment 2 2 in the bit time.
FlexCAN Table 25-15. Mask examples for Normal/Extended Messages 1 2 3 4 5 6 7 Base ID ID28.................
FlexCAN 31 21 Field MID[28:18] Reset 20 19 — 18 17 16 MID[17:15] 1111_1111_1110_1111 R/W R/W 15 1 Field MID[14:0] Reset 0 — 1111_1111_1111_1110 R/W R/W Address IPSBAR + 0x1C_0010 (RXGMASK), 0x1C_0014 (RX14MASK), 0x1C_0018 (RX15MASK) Figure 25-12. Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions Bits Name 31–21 MID 20 — Reserved. The IDE bit of a received frame is always compared.
FlexCAN 15 Field 14 BITERR 13 12 ACKERR CRCERR Reset 10 9 FORMERR STUFFERR TXWARN 8 RXWARN 0000_0000 R/W Field 11 R 7 6 IDLE TX/RX 5 4 FCS Reset 3 2 1 0 — BOFFINT ERRINT WAKEINT 0000_0000 R/W R/W R Address IPSBAR + 0x1C_0020 Figure 25-13. FlexCAN Error and Status Register (ESTAT) Table 25-17 describes the ESTAT fields. Table 25-17. ESTAT Field Descriptions Bits Name Description 15–14 BITERR Transmit bit error.
FlexCAN Table 25-17. ESTAT Field Descriptions (continued) Bits Name 8 RXWARN 7 IDLE 6 TX/RX Transmit/receive status. The TX/RX bit indicates when the FlexCAN module is transmitting or receiving a message. TX/RX has no meaning when IDLE = 1. 0 The FlexCAN is receiving a message if IDLE = 0. 1 The FlexCAN is transmitting a message if IDLE = 0. 5–4 FCS Fault confinement state. The FCS[1:0] field describes the state of the FlexCAN.
FlexCAN The interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0 (IMASK_L). The register can be accessed by the master as a 16-bit register, or each byte can be accessed individually using an 8-bit (byte) access cycle.
FlexCAN Field 15 14 13 12 11 10 9 8 BUF15I BUF14I BUF13I BUF1I BUF11I BUF10I BUF9I BUF8I Reset 0000_0000 R/W Field R/w 7 6 5 4 3 BUF7I BUF6I BUF5I BUF4I BUF3I Reset 0 BUF2I BUF1I BUF0I 0000_0000 R/W R/W Address IPSBAR + 0x1C_0024 Figure 25-15. Interrupt Flag Register (IFLAG) Table 25-19 describes the IFLAG fields. Table 25-19. IFLAG Field Descriptions Bits Name Description 15–0 BUFnI IFLAG contains one interrupt flag bit per buffer.
FlexCAN 25.5.12 FlexCAN Transmit Error Counter (TXECTR) 7 0 Field TXECTR Reset 0000_0000 R/W R Address IPSBAR + 0x1C_0028 Figure 25-17. FlexCAN Transmit Error Counter (TXECTR) Table 25-21 describes the TXECTR fields. Table 25-21. TXECTR Field Descriptions Bits Name Description 7–0 TXECT Transmit error counter. Indicates the current transmit error count as defined in the CAN protocol. See R Section 25.4.9, “FlexCAN Error Counters” for more details.
Chapter 26 General Purpose I/O Module 26.1 Introduction Many of the pins associated with the external interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
General Purpose I/O Module PAS5 / URXD2 D[31:24] / PA[7:0] PORT A D[23:16] / PB[7:0] PORT B D[15:8] / PC[7:0] D[7:0] / PD[7:0] A[23:21] / PF[7:5] / CS[6:4] SDA / PAS1 / URXD2 PORT AS PORT NQ1 1 PORT C PORT QA PORT D PORT QB1 SCL / PAS0 / UTXD2 IRQ[7:1] / PNQ[7:1] AN56 / PQA4 / ETRIG2 AN55 / PQA3 / ETRIG1 AN53 / PQA1 / MA1 AN52 / PQA0 / MA0 AN3 / PQB3 / ANZ AN2 / PQB2 / ANY AN1 / PQB1 / ANX AN0 / PQB0 / ANW QSPI_CS[3:0] / PQS[6:3] SIZ1 / PE3 / SYNCA SIZ0 / PE2 / SYNCB TS / PE1 / SYNCA TIP /
General Purpose I/O Module EMDIO / PAS5 / URXD2 D[31:24] / PA[7:0] PORT A D[23:16] / PB[7:0] PORT B D[15:8] / PC[7:0] D[7:0] / PD[7:0] A[23:21] / PF[7:5] / CS[6:4] SDA / PAS1 / URXD2 PORT AS PORT NQ1 1 PORT C PORT QA PORT D PORT QB1 SCL / PAS0 / UTXD2 IRQ[7:1] / PNQ[7:1] AN56 / PQA4 / ETRIG2 AN55 / PQA3 / ETRIG1 AN53 / PQA1 / MA1 AN52 / PQA0 / MA0 AN3 / PQB3 / ANZ AN2 / PQB2 / ANY AN1 / PQB1 / ANX AN0 / PQB0 / ANW QSPI_CS[3:0] / PQS[6:3] SIZ1 / PE3 / SYNCA SIZ0 / PE2 / SYNCB TS / PE1 / SYN
General Purpose I/O Module 26.1.1 Overview The ports module controls the configuration for various external pins, including those used for: • External bus accesses • Chip selects • Debug data • Processor status • Ethernet data and control (not present on the MCF5214 and MCF5216) • FlexCAN transmit/receive data • I2C serial control • QSPI • SDRAM control • 32-bit DMA timers • UART transmit/receive 26.1.
General Purpose I/O Module Table 26-1.
General Purpose I/O Module Table 26-1.
General Purpose I/O Module Table 26-1.
General Purpose I/O Module Table 26-2. Ports Module Memory Map (continued) IPSBAR + Offset 31–24 23–16 15–8 7–0 Access1 0x10_0008 PORTJ PORTDD PORTEH (Reserved on MCF521x) PORTEL S/U 0x10_000C PORTAS PORTQS PORTSD PORTTC S/U 0x10_0010 PORTTD PORTUA Reserved2 S/U MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
General Purpose I/O Module Table 26-2.
General Purpose I/O Module 26.3.2 26.3.2.1 Register Descriptions Port Output Data Registers (PORTn) The PORTn registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-3. The remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in Figure 26-4, Figure 26-5, and Figure 26-6. At reset, all bits in the PORTn registers are set.
General Purpose I/O Module 7 4 Field — Reset 3 2 1 0 PORTn3 PORTn2 PORTn1 PORTn0 0000_1111 R/W: R Address R/W IPSBAR + 0x10_000F (PORTTC), 0x10_0010 (PORTTD), 0x10_0011 (PORTUA) Figure 26-6. Port Output Data Registers (4-bit) PORTn bits are described in Table 26-3. Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions 26.3.2.
General Purpose I/O Module Field 7 6 — DDRn6 0 DDRn5 DDRn4 Reset R/W: DDRn3 DDRn2 DDRn1 DDRn0 0000_0000 R R/W Address IPSBAR + 0x10_0021(DDRQS) Figure 26-8. Port Data Direction Register (7-bit) 7 Field 6 — 5 4 3 2 1 0 DDRn5 DDRn4 DDRn3 DDRn2 DDRn1 DDRn0 Reset 0000_0000 R/W: R R/W Address IPSBAR + 0x10_0020 (DDRAS), 0x10_0022 (DDRSD) Figure 26-9.
General Purpose I/O Module 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn) The PORTnP/SETn registers reflect the current pin states and control the setting of output pins when the pin is configured for digital I/O. Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-11. The remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in Figure 26-12, Figure 26-13, and Figure 26-14. The PORTnP/SETn registers are read/write.
General Purpose I/O Module 7 4 3 2 1 0 Field — PORTnP3/ PORTnP2/ PORTnP1/ PORTnP0/ SETn3 SETn2 SETn1 SETn0 Reset 0000 Current Pin State R/W: — R/W Address IPSBAR + 0x10_0037 (PORTTCP/SETTC), 0x10_0038 (PORTTDP/SETTD), 0x10_0039 (PORTUAP/SETUA) Figure 26-14. Port Pin Data/Set Data Registers (4-bit) PORTnP/SETn bits are described in Table 26-5. Table 26-5.
General Purpose I/O Module Field 7 6 5 4 3 2 1 0 — CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 Reset R/W: 0000_0000 R R/W Address IPSBAR + 0x10_0049 (CLRQS) Figure 26-16. Port Clear Output Data Register (7-bit) 7 Field 6 — 5 4 3 2 1 0 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 Reset 0000_0000 R/W: R R/W Address IPSBAR + 0x10_0048 (CLRAS), 0x10_004A (CLRSD) Figure 26-17.
General Purpose I/O Module 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR) The PBCDPAR controls the pin function of ports B, C, and D. The PBCDPAR register is read/write. 7 Field 6 PBPA Reset See Note 1 R/W: R/W 1 5 0 PCDPA — See Note 1 00_0000 R/W R Address IPSBAR + 0x10_0050 Figure 26-19. Port B/C/D Pin Assignment Register (PBCDPAR) 1 Reset state determined during reset configuration as shown in Table 26-8. Table 26-7.
General Purpose I/O Module 26.3.2.6 Port E Pin Assignment Register (PEPAR) The PEPAR controls the pin function of port E. The PEPAR register is read/write.
General Purpose I/O Module Table 26-9. PEPAR Field Descriptions (continued) Bits Name Description 6 PEPA3 Port E pin assignment 3 This bit configures the port E3 pin for its alternate function (SYNCA) or digital I/O. 1 Port E3 pin configured for alternate function (SYNCA) 0 Port E3 pin configured for digital I/O NOTE: The SIZ1 primary function on the port E3 pin is enabled by the SZEN bit in the CCR register.
General Purpose I/O Module 26.3.2.7 Port F Pin Assignment Register (PFPAR) The PFPAR controls the pin function of port F[7:5]. Field 7 6 PFPA7 PFPA6 5 4 0 PFPA5 — 1 Reset See Note 1 0_0000 R/W: R/W R Address IPSBAR + 0x10_0051 Figure 26-21. Port F Pin Assignment Register (PFPAR) 1 Reset state determined during reset configuration. PFPAn = 1 in master mode and 0 in all other modes. Table 26-11. PFPAR Field Descriptions Bits Name Description 7 PFPA7 Port F pin assignment 1.
General Purpose I/O Module 26.3.2.8 Port J Pin Assignment Register (PJPAR) The PJPAR controls the pin function of port J. Field 7 6 5 4 3 2 1 0 PJPA7 PJPA6 PJPA5 PJPA4 PJPA3 PJPA2 PJPA1 PJPA0 Reset See Note 1 R/W: R/W Address 1 IPSBAR + 0x10_0054 Figure 26-22. Port J Pin Assignment Register (PJPAR) 1 Reset state determined during reset configuration. PJPAn = 1 in master mode and 0 in all other modes. Table 26-12.
General Purpose I/O Module 26.3.2.9 Port SD Pin Assignment Register (PSDPAR) The PSDPAR controls the pin function of port SD. 7 Field 6 0 PSDPA — 1 000_0000 Reset See Note 1 R/W: R/W R Address IPSBAR + 0x10_0055 Figure 26-23. Port SD Pin Assignment Register (PSDPAR) 1 Reset state determined during reset configuration. PJPAn = 1 in master mode and 0 in all other modes. Table 26-13. PSDPAR Field Descriptions Bits Name Description 7 PSDPA Port SD pin assignment.
General Purpose I/O Module Table 26-14. PASPAR Field Descriptions Bits Name Description 15–12 — 11–10 PASPA5 Port AS pin assignment 5. These bits configure the AS5 pin for its primary function (EMDIO), alternate function (URXD2), or digital I/O. 0x Port AS5 pin configured for digital I/0 10 Port AS5 pin configured for alternate function (URXD2) 11 Port AS5 pin configured for primary function (EMDIO) Note: Setting 11 is reserved for the MCF5214 and MCF5216. 9-8 PASPA4 Port AS pin assignment 4.
General Purpose I/O Module Field 7 6 5 PEHPA PELPA 0 — Reset 0000_0000 R/W: R/W R Address IPSBAR + 0x10_0058 Figure 26-25. Port EH/EL Pin Assignment Register (PEHLPAR) Table 26-15. PEHLPAR Field Descriptions Bits Name Description 7 PEHPA Port EH pin assignment. This bit configures the port EH pins for its primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) or digital I/O.
General Purpose I/O Module Table 26-16. PQSPAR Field Description (continued) Bits Name Description 5 PQSPA5 Port QS pin assignment 5. This bit configures the port QS5 pin for its primary function (QSPI_CS2) or digital I/O. 1 Port QS5 pin configured for primary function (QSPI_CS2) 0 Port QS5 pin configured for digital I/O 4 PQSPA4 Port QS pin assignment 4. This bit configures the port QS4 pin for its primary function (QSPI_CS1) or digital I/O.
General Purpose I/O Module Table 26-17. PTCPAR Field Descriptions Bits Name Description 7–6 PTCPA3 Port TC pin assignment 3. This field configures the port TC3 pin for its primary function (DTIN3), alternate 1 function (URTS1), alternate 2 function (URTS0) or digital I/O.
General Purpose I/O Module Table 26-18. PTDPAR Field Descriptions Bits Name Description 7–6 PTDPA3 Port TD pin assignment 3. This field configures the port TD3 pin for its primary function (DTIN1), alternate 1 function (URTS1), alternate 2 function (URTS0) or digital I/O.
General Purpose I/O Module Table 26-19. PUAPAR Field Descriptions (continued) Bits Name 2 PUAPA2 Port UA pin assignment 2. This bit configures the port UA2 pin for its primary function (UTXD1) or digital I/O. 1 Port UA2 pin configured for primary function (UTXD1) 0 Port UA2 pin configured for digital I/O 1 PUAPA1 Port UA pin assignment 1. This bit configures the port UA1 pin for its primary function (URXD0) or digital I/O.
General Purpose I/O Module CLKOUT INPUT PIN REGISTER PIN DATA Figure 26-30. Digital Input Timing Data written to the PORTn register of any pin configured as a digital output is immediately driven to its respective pin, as shown in Figure 26-31. CLKOUT OUTPUT DATA REGISTER OUTPUT PIN Figure 26-31. Digital Output Timing 26.5 Initialization/Application Information The initialization for the ports module is done during reset configuration.
Chapter 27 Chip Configuration Module (CCM) The chip configuration module (CCM) controls the chip configuration and operating mode. 27.1 Features The CCM performs these operations.
Chip Configuration Module (CCM) 27.3 Block Diagram Reset Configuration Output Pad Strength Selection Chip Mode Selection Clock Mode Selection Boot Device / Port Size Selection Chip Select Configuration Chip Configuration Register Reset Configuration Register Chip Identification Register Chip Test Register Figure 27-1. Chip Configuration Module Block Diagram 27.4 Signal Descriptions Table 27-1 provides an overview of the CCM signals. Table 27-1. Signal Properties Name 27.4.
Chip Configuration Module (CCM) 27.4.3 D[26:24, 21, 19:16] (Reset Configuration Override) If the external RCON pin is asserted during reset, then the states of these data pins during reset determine the chip mode of operation, boot device, clock mode, and certain module configurations after reset. 27.5 Memory Map and Registers This subsection provides a description of the memory map and registers. 27.5.
Chip Configuration Module (CCM) 4 Accessing an unimplemented address has no effect and causes a cycle termination transfer error. NOTE To safeguard against unintentionally activating test logic, write 0x0000 to the above reserved location during initialization (immediately after reset) to lock out test features. Setting any bits in the CCR may lead to unpredictable results. 27.5.3 Register Descriptions The following subsection describes the CCM registers. 27.5.3.
Chip Configuration Module (CCM) Table 27-4. CCR Field Descriptions (continued) Bits Name 4 — 3 BME Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles. 0 Bus monitor disabled for external bus cycles. 1 Bus monitor enabled for external bus cycles. Table 27-2 shows the read/write accessibility of this write-once bit. 2–0 BMT Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
Chip Configuration Module (CCM) Table 27-5. RCON Field Descriptions (continued) Bits Name 4–3 BOOTPS Boot port size. Reflects the default selection for the boot port size if the boot device is configured to be external. 00 Internal (32 bits) (This is the value used for this device.) 01 16 bits 10 8 bits 11 32 bits The default function of the boot port size can be overridden during reset configuration. 2 BOOTSEL Boot select. Reflects the default selection for the boot device.
Chip Configuration Module (CCM) 5. Clock mode selections 6. Chip select configuration These functions are described here. 27.6.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states. Table 27-7 shows the states of the external pins while in reset. Table 27-7.
Chip Configuration Module (CCM) Table 27-8.
Chip Configuration Module (CCM) NOTE When Flash security is enabled, the chip will boot in single chip mode regardless of the external reset configuration. Table 27-9.
Chip Configuration Module (CCM) Table 27-11. Clock Mode Selection Synthesizer Status Register (SYNSR) Clock Mode 27.6.6 CLKMOD[1:0] PLLSEL PLLREF PLLMOD External clock mode (PLL disabled) 00 0 0 0 1:1 PLL mode 01 0 0 1 Normal PLL mode, external clock reference 10 1 0 1 Normal PLL mode, crystal oscillator reference 11 1 1 1 Chip Select Configuration The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC field of the CCR.
Chapter 28 Queued Analog-to-Digital Converter (QADC) The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive approximation converter. Up to eight analog input channels can be supported using internal multiplexing. A maximum of 18 input channels can be supported in the expanded, externally multiplexed mode. The QADC consists of an analog front-end and a digital control subsystem. The analog section includes input pins, an analog multiplexer, and sample and hold analog circuits.
Queued Analog-to-Digital Converter (QADC) 28.2 Block Diagram External MUX Address Analog Power Inputs 8 Analog Channels (18 with External MUXing) Reference Inputs External Triggers Analog Input MUX and Digital Signal Functions 10-bit Analog-to-Digital Converter Digital Control 64-Entry Queue of 10-bit Conversion Command Words (CCWs) 64-Entry Table of 10-bit Results 10-bit to 16-bit Result Alignment IPBUS Interface Figure 28-1. QADC Block Diagram 28.
Queued Analog-to-Digital Converter (QADC) • If during the execution of the current conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occurs, the QADC freezes immediately. When the QADC enters debug mode while a queue is active, the current CCW location of the queue pointer is saved.
Queued Analog-to-Digital Converter (QADC) 28.4.1.1 Port QA Analog Input Signals When used as analog inputs, the four port QA signals are referred to as AN[56:55, 53:52].
Queued Analog-to-Digital Converter (QADC) 28.4.2.2 Port QB Digital I/O Signals Port QB signals are referred to as PQB[3:0] when used as a 4-bit digital input/output port. In addition to functioning as analog input signals, the port QB signals are also connected to the input of a synchronizer during reads and may be used as general-purpose digital inputs when the applied voltages meet VIH and VIL requirements.
Queued Analog-to-Digital Converter (QADC) 28.4.6 Voltage Reference Signals VRH and VRL are the dedicated input signals for the high and low reference voltages. Separating the reference inputs from the power supply signals allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. NOTE VRH and VRL must be set to VDDA and VSSA potential, respectively. For more information, refer to Section 28.
Queued Analog-to-Digital Converter (QADC) Table 28-2. QADC Memory Map (continued) IPSBAR + Offset MSB LSB Access1 0x19_0014– 0x19_01fe Reserved(3) — 0x19_0200– 0x19_027e Conversion Command Word Table (CCW) S/U 0x19_0280– 0x19_02fe Right Justified, Unsigned Result Register (RJURR) S/U 0x19_0300– 0x19_037e Left Justified, Signed Result Register (LJSRR) S/U 0x19_0380– 0x19_03fe Left Justified, Unsigned Result Register (LJURR) S/U 1 S = CPU supervisor mode access only.
Queued Analog-to-Digital Converter (QADC) Table 28-3. QADCMCR Field Descriptions Bit(s) Name 15 QSTOP Stop enable. 1 Force QADC to idle state. 0 QADC operates normally. 14 QDBG Debug enable. 1 Finish any conversion in progress, then freeze in debug mode 0 QADC operates normally. 13–8 — 7 SUPV 6–0 — 28.6.2 Description Reserved, should be cleared. Supervisor/unrestricted data space.
Queued Analog-to-Digital Converter (QADC) 7 6 5 4 3 2 1 0 PQB3 (AN3) (ANZ) PQB2 (AN2) (ANY) PQA1 (AN1) (ANX) PQA0 (AN0) (ANW) Field — Reset 0000 See Note R/W: R R/W Address IPSBAR + 0x19_0007 Figure 28-5. QADC Port QB Data Register (PORTQB) Note: The reset value for these fields is the current signal state if DDR is an input; otherwise, they are undefined. 28.6.
Queued Analog-to-Digital Converter (QADC) 7 6 Field 5 4 — Reset 3 2 1 0 DDQB3 DDQB2 DDQB1 DDQB0 0000_0000 R/W R Address IPSBAR + 0x19_0009 Figure 28-7. Port QB Data Direction Register (DDRQB) 28.6.5 Control Registers This subsection describes the QADC control registers. 28.6.5.1 QADC Control Register 0 (QACR0) QACR0 establishes the QADC sampling clock (QCLK) with prescaler parameter fields and defines whether external multiplexing is enabled.
Queued Analog-to-Digital Converter (QADC) Table 28-4. QACR0 Field Descriptions (continued) Bit(s) Name 11–7 — 6–0 QPR Description Reserved, should be cleared. Prescaler clock divider. Selects the system clock divisor to generate the QADC clock as Table 28-5 shows. The resulting QADC clock rate can be given as: fQCLK = fSYS 2(QPR[6:0] + 1) where: 1 ≤ QPR[6:0] ≤ 127. If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler divisor is 2.
Queued Analog-to-Digital Converter (QADC) Table 28-5.
Queued Analog-to-Digital Converter (QADC) Table 28-6. QACR1 Field Descriptions Bit(s) Name Description 15 CIE1 Queue 1 completion interrupt enable. Enables an interrupt request upon completion of queue 1. The interrupt request is initiated when the conversion is complete for the last CCW in queue 1. 1 Enable queue 1 completion interrupt. 0 Disable queue 1 completion interrupt. 14 PIE1 Queue 1 pause interrupt enable. Enables an interrupt request when queue 1 enters the pause state.
Queued Analog-to-Digital Converter (QADC) Table 28-7. Queue 1 Operating Modes (continued) MQ1[12:8] 28.6.5.
Queued Analog-to-Digital Converter (QADC) for queue 1 and a trigger event occurs for queue 1 with BQ2 set to 0. Queue 1 execution starts momentarily, but is terminated after CCW0 is read. No conversions occur. The BQ2[6:0] pointer may be changed dynamically to alternate between queue 2 scan sequences. A change in BQ2 after queue 2 has begun or when queue 2 has a trigger pending does not affect queue 2 until it is started again.
Queued Analog-to-Digital Converter (QADC) Table 28-8. QACR2 Field Descriptions Bit(s) Name Description 15 CIE2 Queue 2 completion software interrupt enable. Enables an interrupt request upon completion of queue 2. The interrupt request is initiated when the conversion is complete for the last CCW in queue 2. 1 Enable queue 2 completion interrupt. 0 Disable queue 2 completion interrupt. 14 PIE2 Queue 2 pause interrupt enable. Enables an interrupt request when queue 2 enters the pause state.
Queued Analog-to-Digital Converter (QADC) Table 28-9. Queue 2 Operating Modes (continued) MQ2[12:8] 28.6.
Queued Analog-to-Digital Converter (QADC) • When the currently completed CCW is in the last location of the CCW RAM. Once PFn is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. However, a special case occurs when the CCW with the pause bit set is the last CCW in a queue; queue execution is complete. The queue status becomes idle, not paused, and both the pause and completion flags are set.
Queued Analog-to-Digital Converter (QADC) A queue is in the active state when a valid queue operating mode is selected, when the selected trigger event has occurred, or when the QADC is performing a conversion specified by a CCW from that queue. Only one queue can be active at a time. One or both queues can be in the paused state. A queue is paused when the previous CCW executed from that queue had the pause bit set. The QADC does not execute any CCWs from the paused queue until a trigger event occurs.
Queued Analog-to-Digital Converter (QADC) Field 7 6 5 4 3 2 1 0 QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0 Reset 0000_0000 R/W: R Address IPSBAR + 0x19_0010, 0x19_0011 Figure 28-11. QADC Status Register 0 (QASR0) Table 28-10. QASR0 Field Descriptions Bit(s) Name Description 15, 13 CFn Queue completion flag. Indicates that a queue scan has been completed.
Queued Analog-to-Digital Converter (QADC) Table 28-10. QASR0 Field Descriptions (continued) Bit(s) Name Description 9–6 QS Queue status. Indicates the current condition of queue 1 and queue 2. The two most significant bits are associated primarily with queue 1, and the remaining two bits are associated with queue 2. Because the priority scheme between the two queues causes the status to be interlinked, the status bits must be considered as one 4-bit field.
Queued Analog-to-Digital Converter (QADC) Table 28-12. Queue Status (continued) QS[9:6] Queue 1/Queue 2 States 0111 Queue 1 paused, queue 2 trigger pending 1000 Queue 1 active, queue 2 idle 1001 Queue 1 active, queue 2 paused 1010 Queue 1 active, queue 2 suspended 1011 Queue 1 active, queue 2 trigger pending 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Queued Analog-to-Digital Converter (QADC) Q2 Trigger Event Q1 Trigger Event Q1 Idle/ Q2 Idle Q2 Complete Q1 Idle/ Q2 Active Q1 Complete Q1 Active/ Q2 Idle Delayed Transition Q2 Pause Bit Set Q1 Pause Bit Set Q1 Idle/ Q2 Trigger Pending (Temporary) Q2 Trigger Event Q2 Trigger Event Q1 Trigger Event Q1 Trigger Event Q1 Paused/ Q2 Idle Q1 Complete Q1 Complete Q1 Idle/ Q2 Paused Q1 Trigger Event Q1 Active/ Q2 Trigger Pending Q1 Active/ Q2 Suspended Q1 Paused/ Q2 Trigger Pending (Temporary) Q
Queued Analog-to-Digital Converter (QADC) 7 6 Field — 5 4 3 2 1 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20 Reset 0011_1111 R/W: R Address IPSBAR + 0x19_0012, 0x19_0013 Figure 28-13. QADC Status Register 1 (QASR1) Table 28-13. QASR1 Field Descriptions Bit(s) Name 15–14 — 13–8 CWPQ1 7–6 — 5–0 CWPQ 28.6.7 Description Reserved, should be cleared. Queue 1 command word pointer. Points to the last queue 1 CCW executed.
Queued Analog-to-Digital Converter (QADC) Field 7 6 5 4 3 2 1 0 IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0 Reset Undefined R/W: R Address IPSBAR + 0x19_0200, 0x19_027e Figure 28-14. Conversion Command Word Table (CCW) Table 28-14. CCW Field Descriptions Bit(s) Name Description 15–10 — Reserved, should be cleared. 9 P Pause. Allows subqueues to be created within queue 1 and queue 2.
Queued Analog-to-Digital Converter (QADC) Table 28-15. Input Sample Times IST[1:0] Input Sample Times 00 Input sample time = QCLK period × 2 01 Input sample time = QCLK period × 4 10 Input sample time = QCLK period × 8 11 Input sample time = QCLK period × 16 Table 28-16.
Queued Analog-to-Digital Converter (QADC) 1 All channels not listed are reserved or unimplemented and return undefined results. 28.6.8 Result Registers The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is written by the QADC after completing an analog conversion specified by the corresponding CCW table entry. 28.6.8.
Queued Analog-to-Digital Converter (QADC) Table 28-19. LJSRR Field Descriptions Bit(s) Name Description 15 S The left justified, signed format corresponds to a half-scale, offset binary, two’s complement data format. Conversion values corresponding to 1/2 full scale, 0x0200, or higher are interpreted as positive values and have a sign bit of 0. An unsigned, right justified conversion of 0x0200 would be represented as 0x0000 in this signed register, where the sign = 0 and the result = 0.
Queued Analog-to-Digital Converter (QADC) Specifically, this means that while the QADC is operating, the data in the result registers can change from one read to the next. Simply initiating a read of one result register will not prevent another from being updated with a new conversion result. Thus, to read any given number of result registers coherently, the queue or queues capable of modifying these registers must be inactive.
Queued Analog-to-Digital Converter (QADC) AN1 AN3 AN5 AN7 MUX MUX AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 Port QB AN0 AN2 AN4 AN6 AN55/ETRIG1PQA3 AN56/ETRIG2/PQA4 AN16 AN18 AN20 AN22 AN17 AN19 AN21 AN23 Port QA AN52/MA0/PQA0 AN53/MA1/PQA1 MUX MUX Figure 28-18. External Multiplexing Configuration When externally multiplexed mode is selected, the QADC automatically drives the MA output signals from the channel number in each CCW.
Queued Analog-to-Digital Converter (QADC) Figure 28-18 shows that the two MA signals may also be analog input signals. When external multiplexing is selected, none of the MA signals can be used for analog or digital inputs. They become multiplexed address outputs and are unaffected by DDRQA[1:0]. 28.7.2.2 Module Version Options The number of available analog channels varies, depending on whether external multiplexing is used.
Queued Analog-to-Digital Converter (QADC) 16 PQA4 4 Chan. Decode & MUX 16:1 CHAN[5:0] 6 PQA0 10-bit A/D Converter Input Bias Circuit Internal Channel Decode Sample Buffer PQB0 PowerDown State Machine & Logic CSAMP VRH VRL VSSA 2 SAR Timing 10 Analog Power Comparator QCLK IST Start Conv End OF Conv SAR[9:0] 10 VDDA STOP RST 10 Signals From/to Queue Control Logic PQB3 Successive Approximation Register Figure 28-19. QADC Analog Subsystem Block Diagram 28.7.3.
Queued Analog-to-Digital Converter (QADC) Buffer Sample Time: 2 Cycles Final Sample Time: n Cycles (2,4,8,16) Resolution Time: 10 Cycles QCLK Sample Time Successive Approximation Resolution Sequence Figure 28-20. Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the CCW, the timing changes to that shown in Figure 28-21. See Section 28.6.7, “Conversion Command Word Table (CCW) for more information on the BYP field.
Queued Analog-to-Digital Converter (QADC) 28.7.3.6 Bias The bias circuit is controlled by the STOP signal to power-up and power-down all the analog circuits. 28.7.3.7 Successive Approximation Register (SAR) The input of the SAR is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time, starting with the MSB.
Queued Analog-to-Digital Converter (QADC) • • completion or the paused state, queue 2 begins executing again. The programming of the RESUME bit in QACR2 determines which CCW is executed in queue 2. When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and the queue 2 status is changed to trigger pending. When subqueues are paused The pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues.
Queued Analog-to-Digital Converter (QADC) Conversion Command Word (CCW) Table Result Word Table P 00 0 Beginning of Queue 1 00 0 0 1 Pause 0 0 0 1 Pause 0 P • • • • • 0 0 BQ2 0 1 End of Queue 1 Channel Select, Sample, Hold, A/D Conversion • Beginning of Queue 2 Pause 0 1 Pause 0 1 Pause 0 63 • • • • P • • 1 Pause 0 End of Queue 2 63 Figure 28-22.
Queued Analog-to-Digital Converter (QADC) The following paragraphs and figures outline the prioritizing criteria used to determine which conversion occurs in each overlap situation. NOTE Each situation in Figure 28-23 through Figure 28-33 is labeled S1 through S19. In each diagram, time is shown increasing from left to right. The execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string of rectangles representing the execution time of each CCW in the queue.
Queued Analog-to-Digital Converter (QADC) The first three examples in Figure 28-23 through Figure 28-25 (S1, S2, and S3) show what happens when a new trigger event is recognized before the queue has completed servicing the previous trigger event on the same queue. In situation S1 (Figure 28-23), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event.
Queued Analog-to-Digital Converter (QADC) T1 Q1: T1 C1 T1 C2 C3 T2 TOR1 T2 TOR1 C1 ACTIVE QS: PF2 PAUSE 1001 0101 CF2 IDLE ACTIVE 0110 0100 C4 TOR2 ACTIVE 1000 0000 C3 PAUSE IDLE Q2: T2 CF1 C2 TOR2 IDLE C4 T2 PF1 Q2: Q1: T1 0001 ACTIVE IDLE 0010 0000 Figure 28-25. CCW Priority Situation 3 The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced.
Queued Analog-to-Digital Converter (QADC) T1 Q1: T1 C1 C2 T2 T2 C3 T2 T2 PF1 Q2: C1 Q2: QS: IDLE IDLE 0110 CF2 ACTIVE ACTIVE ACTIVE 1000 1011 C4 TOR2 PAUSE TRIG 0000 C3 PF2 ACTIVE CF1 C2 TOR2 Q1: C4 PAUSE IDLE TRIG ACTIVE IDLE 0010 0000 0101 1001 1011 Figure 28-27. CCW Priority Situation 5 The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during queue 2 execution.
Queued Analog-to-Digital Converter (QADC) . T1 Q1: T1 C1 C2 T2 Q2: C3 PF1 C1 C1 C4 T2 C1 CF1 C3 C2 C3 C4 CF2 PF2 IDLE Q1: ACTIVE Q2: IDLE ACTIVE QS: 0000 0010 SUSPEND PAUSE ACTIVE ACTIVE PAUSE ACT 1010 0110 SUSPEND 0101 0110 1010 IDLE ACTIVE IDLE 0010 0000 Figure 28-29. CCW Priority Situation 7 Situations S8 and S9 (Figure 28-30 and Figure 28-31) repeat the same two situations with the RESUME bit set to a 1.
Queued Analog-to-Digital Converter (QADC) T1 Q1: T1 C1 C2 T2 Q2: C3 PF1 C1 C1 C2 C4 T2 CF1 C4 C3 C2 C4 CF2 PF2 ACTIVE IDLE Q1: Q2: IDLE ACTIVE QS: 0000 0010 PAUSE ACTIVE SUSPEND ACT PAUSE ACTIVE 1010 RESUME=1 IDLE SUSPEND ACT 0110 0110 0101 IDLE 1010 0000 0010 Figure 28-31.
Queued Analog-to-Digital Converter (QADC) T1 Q1: C1 T2 Q2: T1 C2 T2 C1 PF1 C2 IDLE QS: 0000 ACTIVE C3 C4 PAUSE RESUME = 1 C4 CF2 ACTIVE ACTIVE 0110 0101 1010 CF1 TOR2 SUSPEND ACT PAUSE 0010 C4 T2 PF2 ACTIVE IDLE Q2: T2 C2 TOR2 Q1: C3 0110 IDLE SUSPEND ACT 1010 0010 IDLE 0000 Figure 28-33. CCW Priority Situation 11 The previous situations cover normal overlap conditions that arise with asynchronous trigger events on the two queues.
Queued Analog-to-Digital Converter (QADC) FREEZE T2 Q2: C1 C2 C3 C4 CF2 Figure 28-35. CCW Freeze Situation 13 TRIGGERS IGNORED FREEZE T1 T1 T1 C1 Q1: C2 C3 C4 T2 T2 CF1 Figure 28-36. CCW Freeze Situation 14 TRIGGERS IGNORED FREEZE T2 T2 T2 C1 Q2: C2 C3 C4 T1 T1 CF2 Figure 28-37. . CCW Freeze Situation 15 TRIGGERS IGNORED FREEZE T1 Q1: T1 C1 C2 T1 C3 C4 PF1 CF1 Figure 28-38. CCW Freeze Situation 16 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Queued Analog-to-Digital Converter (QADC) TRIGGERS IGNORED FREEZE T2 T2 Q2: C1 T2 C2 C3 C4 PF2 CF2 Figure 28-39. CCW Freeze Situation 17 FREEZE T1 Q1: C1 C2 C3 C4 T2 CF1 Q2: TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE C1 C2 C3 C4 CF2 Figure 28-40. CCW Freeze Situation 18 FREEZE T1 Q1: C1 C2 C3 T2 Q2: C4 CF1 C1 C2 C3 C4 C4 CF2 Figure 28-41. CCW Freeze Situation 19 28.8.
Queued Analog-to-Digital Converter (QADC) • BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64–127) and a trigger event occurs on queue 2. The end-of-queue condition is recognized immediately, the completion flag is set, and the queue becomes idle. A conversion is not performed. NOTE Multiple end-of-queue conditions may be recognized simultaneously, although there is no change in QADC behavior.
Queued Analog-to-Digital Converter (QADC) 28.8.4 Disabled Mode When disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution. When both queue 1 and queue 2 are disabled, there is no possibility of encountering wait states when accessing CCW table and result RAM. When both queues are disabled, it is safe to change the QCLK prescaler values. 28.8.5 Reserved Mode Reserved mode is available for future mode definitions.
Queued Analog-to-Digital Converter (QADC) 28.8.6.1 Software-Initiated Single-Scan Mode Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting software-initiated single-scan mode and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated internally and the QADC immediately begins execution of the first CCW in the queue. If a pause occurs, another trigger event is generated internally, and then execution continues without pausing.
Queued Analog-to-Digital Converter (QADC) bit should be cleared before another scan of queue 1 is initiated during the next open gate. The start of queue 1 is always the first CCW in the CCW table. Because the gate level is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 28.8.6.
Queued Analog-to-Digital Converter (QADC) In the case of software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other continuous-scan queue operating modes, the selected trigger event must occur before the queue can start. A trigger overrun is captured if a trigger event occurs during queue execution in the externally triggered continuous-scan mode or the periodic timer continuous-scan mode.
Queued Analog-to-Digital Converter (QADC) polarity of the external trigger signal is programmable, so that a mode which begins queue execution on the rising or falling edge can be selected. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When the next external trigger edge is detected, queue execution begins again automatically. Software involvement is not needed between trigger events.
Queued Analog-to-Digital Converter (QADC) trigger events. Because both queues may be triggered by the periodic/interval timer, see Section 28.8.9, “Periodic/Interval Timer for a summary of periodic/interval timer reset conditions. 28.8.8 QADC Clock (QCLK) Generation Figure 28-42 is a block diagram of the QCLK subsystem. The QCLK provides the timing for the A/D converter state machine which controls the timing of the conversion.
Queued Analog-to-Digital Converter (QADC) • • • • Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer. System reset is asserted. Stop mode is enabled. Debug mode is enabled. NOTE Interval timer single-scan mode does not start the periodic/interval timer until the single-scan enable bit is set.
Queued Analog-to-Digital Converter (QADC) Conversion Command Word (CCW) Table 00 Result Word Table Beginning of Queue 1 00 • • • • • • Channel Select, Sample, Hold, A/D Conversion End of Queue 1 Beginning of Queue 2 63 • • • • • • 63 End of Queue 2 10-bit Result, Readable in Three 16-BIT Formats 10-bit Conversion Command Word Format 9 8 [7:6] [5:0] 15 14 13 12 11 10 [9:0] P BYP IST CHAN 0 0 0 0 0 0 RESULT Right-Justified, Unsigned Result P — Pause after Conversion until Next
Queued Analog-to-Digital Converter (QADC) • Resolution During initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. Each CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles.
Queued Analog-to-Digital Converter (QADC) NOTE Although the result RAM can be written, some write operations, like bit manipulation, may not operate as expected because the hardware cannot access a true 16-bit value.
Queued Analog-to-Digital Converter (QADC) VDDA VRH Sample AMP S/H 16 Channels Total Comparator C VSSA VRL Figure 28-44. Equivalent Analog Input Circuitry Because the sample amplifier is powered by VDDA and VSSA, it can accurately transfer input signal levels up to but not exceeding VDDA and down to but not below VSSA. If the input signal is outside of this range, the output from the sample amplifier is clipped. In addition, VRH and VRL must be within the range defined by VDDA and VSSA.
Queued Analog-to-Digital Converter (QADC) 3FF 3FE 3FD 10-bit Result (Hexadecimal) 3FC 3FB 3FA 8 7 6 5 4 3 2 1 0 .010 .020 .030 5.100 5.110 5.120 5.130 Inputs in Volts (VRH = 5.120 V, VRL = 0 V) Figure 28-45. Errors Resulting from Clipping 28.9.3 Conversion Timing Schemes This section contains some conversion timing examples. Figure 28-46 shows the timing for basic conversions where it is assumed that: • Q1 begins with CCW0 and ends with CCW3. • CCW0 has pause bit set.
Queued Analog-to-Digital Converter (QADC) TIME BETWEEN TRIGGERS CONVERSION TIME = 14 QCLKS CONVERSION TIME = 14 QCLKS QCLK TRIG1 EOC QS CWP 0 4 8 LAST CWPQ1 CCW0 LAST Q1 RES 8 CCW1 CCW2 CCW0 CCW1 R0 R1 Figure 28-46. External Positive Edge Trigger Mode Timing with Pause A time separator is provided between the triggers and the end of conversion (EOC). The relationship to QCLK displayed is not guaranteed.
Queued Analog-to-Digital Converter (QADC) At the end of Q1,the completion flag CF1 sets and the queue restarts. If the queue starts a second time and completes, the trigger overrun flag TOR1 sets. TRIG1 (GATE) EOC QS CWP 0 8 LAST 0 CCW0 8 CCW1 CCW0 0 CCW1 CCW2 CCW3 CWPQ1 LAST CCW0 CCW1 CCW0 CCW1 CCW2 CCW3 Q1 RES LAST R0 R1 R0 R1 R2 R3 SSE CF1 PF1 Figure 28-47.
Queued Analog-to-Digital Converter (QADC) 28.9.4 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding. Generally, digital circuits use bypass capacitors on every VDD/VSS signal pair. This applies to analog subsystems and submodules also. Equally important as bypassing is the distribution of power and ground. Analog supplies should be isolated from digital supplies as much as possible.
Queued Analog-to-Digital Converter (QADC) Analog Power Supply AGND PGND +5 V VDDA +5 V VSSA VRL VRH +5 V Digital Power Supply VSS QADC VDD PCB Figure 28-49. Star-Ground at the Point of Power Supply Origin Other suggestions for PCB layout in which the QADC is employed include: • Analog ground must be low impedance to all analog ground points in the circuit. • Bypass capacitors should be as close to the power pins as possible. • The analog ground should be isolated from the digital ground.
Queued Analog-to-Digital Converter (QADC) Figure 28-50 shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative stress conditions. Figure 28-51 shows positive stress conditions can activate a similar PNP transistor. VSTRESS + RSTRESS Iinjn 10 kΩ RSELECTED IIN ANn Signal Under Stress Parasitic Device ANn+1 VIN Adjacent Signal Figure 28-50.
Queued Analog-to-Digital Converter (QADC) 28.9.6 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. Figure 28-52 shows the connection of eight typical analog signal sources to one QADC analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC analog input channel is displayed.
Queued Analog-to-Digital Converter (QADC) Analog Signal Source RSource2 ~ Filtering and Interconnect R Filter2 Typical MUX Chip (MC54HC4051, MC74HC4051, MC54HC4052, MC74HC4052, MC54HC4053, etc.) Interconnect QADC 0.01 μF1 CSource RSource2 ~ C Filter RFilter2 CMUXIN 0.01 μF1 CSource RSource2 ~ C Filter R Filter2 CMUXIN 0.01 μF1 CSource RSource2 C Filter R Filter2 RMUXOUT CMUXIN ~ CMUXOUT 0.01μF1 CSource RSource2 ~ C Filter R Filter2 CPCB CMUXIN CP CSAMP CIn = CP + CSAMP 0.
Queued Analog-to-Digital Converter (QADC) 28.9.7 Analog Input Pins Analog inputs should have low AC impedance at the pins. Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input signal of the device. Ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high-frequency characteristics). This capacitor has two effects: • It helps attenuate any noise that may exist on the input.
Queued Analog-to-Digital Converter (QADC) 28.9.7.1 Settling Time for the External Circuit The values for RSRC, RF, and CF in the user's external circuitry determine the length of time required to charge CF to the source voltage level (VSRC). At time t = 0, VSRC changes in Figure 28-53 while S1 is open, disconnecting the internal circuitry from the external circuitry. Assume that the initial voltage across CF is 0.
Queued Analog-to-Digital Converter (QADC) CAUTION Leakage below 200 nA is obtainable only within a limited temperature range. Table 28-25. Error Resulting from Input Leakage (IOff) Leakage Value (10-Bit Conversions) Source Impedance 100 nA 200 nA 500 nA 1000 nA 1 kΩ — — 0.1 counts 0.2 counts 10 kΩ 0.2 counts 0.4 counts 1 counts 2 counts 100 kΩ 2 counts 4 count 10 counts 20 counts 28.
Queued Analog-to-Digital Converter (QADC) result is written for a CCW with the pause bit set, the queue pause flag is set, and when enabled, an interrupt is requested. Refer to Table 28-26. The pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Queued Analog-to-Digital Converter (QADC) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 29 Reset Controller Module The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. The Low Voltage Detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module. 29.
Reset Controller Module RSTI Pin Power-On Reset RSTO Pin Watchdog Timer Timeout Reset Controller PLL Loss of Clock To Internal Resets PLL Loss of Lock Software Reset LVD Detect Figure 29-1. Reset Controller Block Diagram 29.3 Signals Table 29-1 provides a summary of the reset controller signal properties. The signals are described in the following paragraphs. Table 29-1.
Reset Controller Module Table 29-2. Reset Controller Memory Map 1 2 29.4.1 IPSBAR Offset Bits 7:0 Access1 0x11_0000 RCR S/U 0x11_0001 RSR S/U 0x11_0002 Reserved2 — 0x11_0003 Reserved2 — S/U = supervisor or user mode access. Writes to reserved address locations have no effect and reads return 0s. Reset Control Register (RCR) The RCR allows software control for requesting a reset, for independently asserting the external RSTO pin, and for controlling low-voltage detect (LVD) functions.
Reset Controller Module Table 29-3. RCR Field Descriptions (continued) Bit(s) Name Description 3 LVDIE LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. 1 LVD interrupt enabled 0 LVD interrupt disabled 2 LVDRE LVD reset enable. Controls the LVD reset if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVD reset has priority over LVD interrupt, if both are enabled.
Reset Controller Module Table 29-4. RSR Field Descriptions (continued) Bit(s) Name 3 POR Power-on reset flag. Indicates that the last reset was caused by a power-on reset. 1 Last reset caused by power-on reset 0 Last reset not caused by power-on reset 2 EXT External reset flag. Indicates that the last reset was caused by an external device asserting the external RSTI pin. 1 Last reset state caused by external reset 0 Last reset not caused by external reset 1 LOC Loss-of-clock reset flag.
Reset Controller Module Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system. 29.5.1.1 Power-On Reset At power up, the reset controller asserts RSTO. RSTO continues to be asserted until VDD has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock.
Reset Controller Module 29.5.2 Reset Control Flow The reset logic control flow is shown in Figure 29-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Reset Controller Module 0 1 POR OR LVD Y LOSS OF CLOCK? N 2 LOSS OF LOCK? Y 5 ENABLE BUS MONITOR N 3 RSTI PIN OR WD TIMEOUT OR SW RESET? Y 6 N BUS CYCLE COMPLETE? N 4 ASSERT RSTO AND LATCH RESET STATUS Y 7 ASSERT RSTO AND LATCH RESET STATUS 8 N RSTI NEGATED? Y 9 PLL MODE? Y 9A N PLL LOCKED? Y N 10 12 NEGATE RSTO WAIT 512 CLKOUT CYCLES 11A 11 Y RCON ASSERTED? LATCH CONFIGURATION N Figure 29-4. Reset Control Flow MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Reset Controller Module 29.5.2.1 Synchronous Reset Requests In this discussion, the reference in parentheses refer to the state numbers in Figure 29-4. All cycle counts given are approximate. If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5).
Reset Controller Module 29.5.3.2 Reset Status Flags For a POR reset, the POR and LVD bits in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the POR. If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits along with the LOC and/or LOL bits are set.
Chapter 30 Debug Support This chapter describes the Revision A enhanced hardware debug support. 30.1 Overview The debug module is shown in Figure 30-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PST[3:0], DDATA[3:0] CLKOUT Communication Port DSCLK, DSI, DSO Figure 30-1.
Debug Support 30.2 Signal Description Table 30-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in Section 30.8, “Freescale-Recommended BDM Pinout.” Table 30-1. Debug Module Signals Signal Description Development Serial Clock (DSCLK) Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising CLKOUT edges.
Debug Support branch target address calculation is based on the contents of a program-visible register (variant addressing). DDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5).
Debug Support Table 30-2. Processor Status Encoding (continued) PST[3:0] Definition Hex Binary 0xE 1110 Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped mode is exited. 0xF 1111 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until the processor is restarted or reset.
Debug Support target instruction. The PST can continue with the next instruction before the address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO. 30.
Debug Support 31 31 31 31 31 31 15 7 15 0 AATR Address attribute trigger register ABLR ABHR Address low breakpoint register Address high breakpoint register CSR Configuration/status register DBR DBMR Data breakpoint register Data breakpoint mask register PBR PBMR PC breakpoint register PC breakpoint mask register TDR Trigger definition register 0 15 0 15 0 15 0 15 0 Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
Debug Support Table 30-3. BDM/Breakpoint Registers DRc[4–0] 0x00 Register Name Abbreviation Initial State Page CSR 0x00010_0000 p. 30-10 — — — Configuration/status register 0x01–0x05 Reserved 0x06 Address attribute trigger register AATR 0x0000_0005 p. 30-7 0x07 Trigger definition register TDR 0x0000_0000 p. 30-14 0x08 Program counter breakpoint register PBR — p. 30-13 0x09 Program counter breakpoint mask register PBMR — p.
Debug Support 15 Field RM 14 13 SZM 12 11 TTM Reset 10 8 TMM 7 6 R 5 SZ 4 3 2 TT 0 TM 0000_0000_0000_0101 R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4–0] 0x06 (AATR) Figure 30-5. Address Attribute Trigger Register (AATR) Table 30-5 describes AATR fields. Table 30-5. AATR Field Descriptions Bits Name Description 15 RM Read/write mask.
Debug Support Table 30-5. AATR Field Descriptions (continued) Bits Name 2–0 TM 30.4.3 Description Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type.
Debug Support Table 30-6 describes ABLR fields. Table 30-6. ABLR Field Description Bits 31–0 Name Description Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific addresses are programmed into ABLR. Table 30-7 describes ABHR fields. Table 30-7. ABHR Field Description Bits 31–0 30.4.4 Name Description Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Debug Support Table 30-8 describes CSR fields. Table 30-8. CSR Field Descriptions Bit 31–28 Name Description BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
Debug Support Table 30-8. CSR Field Descriptions (continued) Bit Name 9–8 BTB 7 — 6 NPL 5 IPI 4 SSM 3–0 — 30.4.5 Description Branch target bytes. Defines the number of bytes of branch target address DDATA displays. 00 0 bytes 01 Lower 2 bytes of the target address 10 Lower 3 bytes of the target address 11 Entire 4-byte target address See Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5).” Reserved, should be cleared. Non-pipelined mode.
Debug Support Table 30-9 describes DBR fields. Table 30-9. DBR Field Descriptions Bits Name Description 31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger. Table 30-10 describes DBMR fields. Table 30-10. DBMR Field Descriptions Bits Name Description 31–0 Mask Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
Debug Support 31 0 Field Program Counter Reset — R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 30.5.3.3, “Command Set Descriptions.” DRc[4–0] 0x08 (PBR) Figure 30-9. Program Counter Breakpoint Register (PBR) Table 30-12 describes PBR fields. Table 30-12. PBR Field Descriptions Bits Name Description 31–0 Address PC breakpoint address.
Debug Support NOTE The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13]) before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Debug Support Table 30-14. TDR Field Descriptions (continued) Bits Name 28–22/ 12–6 EDx Description Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints. 28/12 EDLW Data longword. Entire processor’s local data bus. 27/11 EDWL Lower data word. 26/10 EDWU Upper data word. 25/9 EDLL Lower lower data byte. Low-order byte of the low-order word.
Debug Support 1. A catastrophic fault-on-fault condition automatically halts the processor. 2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 30.6.1, “Theory of Operation.” 3.
Debug Support 30.5.2 BDM Serial Interface When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See Table 30-1. The development system serves as the serial communication channel master and must generate DSCLK.
Debug Support . 16 15 0 S Data Field [15:0] Figure 30-13. Receive BDM Packet Table 30-15 describes receive BDM packet fields. Table 30-15. Receive BDM Packet Field Description Bits Name Description 16 S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
Debug Support Table 30-17. BDM Command Summary Command Mnemonic Read A/D register RAREG/ Write A/D register WAREG/ Read memory location Description CPU State1 Section Command (Hex) Read the selected address or data register and return the results through the serial interface. Halted 30.5.3.3.1 0x218 {A/D, Reg[2:0]} Write the data operand to the specified address or data register. Halted 30.5.3.3.
Debug Support 15 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 0 Register Extension Word(s) Figure 30-15. BDM Command Format Table 30-18 describes BDM fields. Table 30-18. BDM Field Descriptions Bit 15–10 Name Description Operation Specifies the command. These values are listed in Table 30-17. 9 0 8 R/W 7–6 Op Size 5–4 00 Reserved, should be cleared. 3 A/D Address/data. Determines whether the register field specifies a data or address register.
Debug Support Commands transmitted to the debug module Command code transmitted during this cycle High-order 16 bits of memory address Low-order 16 bits of memory address Non-serial-related activity READ (LONG) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ READ MEMORY LOCATION Sequence taken if operation has not completed XXX ’NOT READY’ Next Command Code XXX MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ Data used from this transfer Sequence taken
Debug Support NOTE The BDM status bit (S) is 0 for normally completed commands; S = 1 for illegal commands, not-ready responses, and transfers with bus-errors. Section 30.5.2, “BDM Serial Interface,” describes the receive packet format. Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a NOP and return an illegal command response. 30.5.3.3.
Debug Support Command Sequence WAREG/WDREG ??? MS DATA ’NOT READY’ LS DATA ’NOT READY’ XXX BERR NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ Figure 30-20. WAREG/WDREG Command Sequence Operand Data Result Data 30.5.3.3.3 Longword data is written into the specified address or data register. The data is supplied most-significant word first. Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete.
Debug Support Command/Result Formats: 15 12 Byte 11 8 0x1 7 0x9 4 3 0x0 Command 0 0x0 A[31:16] A[15:0] Result Word Command X X X X X X 0x1 X X 0x9 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] Result Longword Command D[15:0] 0x1 0x9 A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 30-21.
Debug Support 30.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Debug Support Command Sequence: WRITE (B/W) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ WRITE (LONG) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 30-24. WRITE Command Sequence Operand Data Result Data 30.5.3.3.
Debug Support NOTE DUMP does not check for a valid address; it is a valid command only when preceded by NOP, READ, or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a dynamically altered.
Debug Support Command Sequence: READ MEMORY LOCATION DUMP (B/W) ??? XXX ’NOT READY’ NEXT CMD RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ READ MEMORY LOCATION DUMP (LONG) ??? XXX ’ILLEGAL’ XXX BERR NEXT CMD ’NOT READY’ XXX ’NOT READY’ NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ NEXT CMD ’NOT READY’ Figure 30-26. DUMP Command Sequence Operand Data: Result Data: 30.5.3.3.6 None Requested data is returned as either a word or longword.
Debug Support 15 12 Byte 11 8 0x1 X Word X 7 4 0xC X X 0x1 X X 3 0x0 X 0 0x0 X D[7:0] 0xC 0x4 0x0 0x8 0x0 D[15:0] Longword 0x1 0xC D[31:16] D[15:0] Figure 30-27.
Debug Support 30.5.3.3.7 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored. 15 12 11 8 0x0 7 0xC 4 3 0x0 0 0x0 Figure 30-29.
Debug Support Command/Result Formats: 15 Command 12 11 8 7 4 3 0 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D[31:16] D[15:0] Figure 30-33. RCREG Command/Result Formats Rc encoding: Table 30-19.
Debug Support Command Sequence: RCREG ??? MS ADDR ’NOT READY’ MS ADDR ’NOT READY’ READ CONTROL REGISTER XXX ’NOT READY’ NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ Figure 30-34. RCREG Command Sequence Operand Data: Result Data: The only operand is the 32-bit Rc control register select field. Control register contents are returned as a longword, most-significant word first.
Debug Support rcreg accn; // read the desired accumulator wcreg #saved_data,macsr;// restore the original macsr ) Likewise, the following BDM sequence is needed to write an accumulator register: BdmWriteACCn ( rcreg macsr; // read macsr contents & save wcreg #0,macsr; // disable all rounding modes wcreg #data,accn; // write the desired accumulator wcreg #saved_data,macsr;// restore the original macsr ) Additionally, it is required that writes to the accumulator extension registers be perf
Debug Support Command Sequence: WCREG ??? MS ADDR ’NOT READY’ MS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE CONTROL REGISTER XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 30-36. WCREG Command Sequence Operand Data: This instruction requires two longword operands. The first selects the register to which the operand data is to be written; the second contains the data. Successful write operations return 0xFFFF.
Debug Support Command Sequence: RDMREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ Figure 30-38. RDMREG Command Sequence Operand Data: Result Data: None The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first. 30.5.3.3.12 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write.
Debug Support 30.6 Real-Time Debug Support The ColdFire Family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate small intrusions into the real-time operation. The debug module provides three types of breakpoints—PC with mask, operand address range, and data with mask.
Debug Support enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered imprecise because several instructions may execute after the triggering address or data is detected. As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception processing begins.
Debug Support complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus. Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint triggers.
Debug Support Table 30-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax addq.l #imm,x addx.l Dy,Dx and.l y,Dx PST = 0x1, {PST = 0xB, DD = source operand} and.l Dy,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} andi.l #imm,Dx PST = 0x1 asl.l {Dy,#imm},Dx PST = 0x1 asr.l {Dy,#imm},Dx PST = 0x1 bitrev.l Dx PST = 0x1 byterev.l Dx PST = 0x1 bcc.
Debug Support Table 30-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax extb.l Dx PST = 0x1 ff1.l Dx PST = 0x1 jmp x PST = 0x5, {PST = [0x9AB], DD = target address} 1 jsr x PST = 0x5, {PST = [0x9AB], DD = target address}, {PST = 0xB , DD = destination operand}1 lea y,Ax PST = 0x1 link.w Ay,#imm PST = 0x1, {PST = 0xB, DD = destination operand} lsl.l {Dy,#imm},Dx PST = 0x1 lsr.l {Dy,#imm},Dx PST = 0x1 move.
Debug Support Table 30-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax rts PST/DDATA PST = 0x1, {PST = 0xB, DD = source operand}, PST = 0x5, {PST = [0x9AB], DD = target address} scc Dx sub.l y,Rx PST = 0x1, {PST = 0xB, DD = source operand} sub.l Dy,x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} subi.l #imm,Dx PST = 0x1 subq.l #imm,x subx.
Debug Support For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5). Table 30-23 shows the PST/DDATA specification for multiply-accumulate instructions. Table 30-23. PST/DDATA Specification for MAC Instructions Instruction Operand Syntax mac.l Ry,Rx,Accx mac.l PST/DDATA PST = 0x1 RyRx,,Rw,Accx PST = 0x1, {PST = 0xB, DD = source operand} mac.
Debug Support Table 30-24. PST/DDATA Specification for Supervisor-Mode Instructions Instruction Operand Syntax rte PST/DDATA PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3},{ PST =0xB, DD =source operand}, PST = 0x5, {[PST = 0x9AB], DD = target address} stldsr.
Debug Support 30.8 Freescale-Recommended BDM Pinout The ColdFire BDM connector, Figure 30-41, is a 26-pin Berg connector arranged 2 x 13.
Debug Support MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 31 IEEE 1149.1 Test Access Port (JTAG) The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing testing. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. Figure 31-1 shows the block diagram of the JTAG module.
IEEE 1149.1 Test Access Port (JTAG) 31.
IEEE 1149.1 Test Access Port (JTAG) Table 31-2. Pin Function Selected Module selected BDM JTAG — Pin Function — BKPT DSI DSO DSCLK TCLK TMS TDI TDO TRST TCLK BKPT DSI DSO DSCLK When one module is selected, the inputs into the other module are disabled or forced to a known logic level as shown in Table 31-3, in order to disable the corresponding module. Table 31-3.
IEEE 1149.1 Test Access Port (JTAG) The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled and DSO changes state. 31.3.1.6 TDO/DSO — Test Data Output / Development Serial Output The TDO pin is the LSB-first data output. Data is clocked out of TDO on the falling edge of TCLK. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states.
IEEE 1149.1 Test Access Port (JTAG) Table 31-4. IDCODE Register Field Descriptions Bits Name 31–28 PRN 27–22 DC Design center. 21–12 PIN Part identification number. Indicate the device number. 11–1 Description Part revision number. Indicate the revision number of the project. JEDEC Joint electron device engineering council ID bits. Indicate the reduced JEDEC ID for Freescale. 0 ID 31.4.2.3 IDCODE register ID.
IEEE 1149.1 Test Access Port (JTAG) 31.5.2 TAP Controller The TAP controller is a state machine that changes state based on the sequence of logical values on the TMS pin. Figure 31-3 shows the machine’s states. The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCLK signal. Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state.
IEEE 1149.1 Test Access Port (JTAG) Table 31-5.
IEEE 1149.1 Test Access Port (JTAG) accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. Both the data capture and the shift operation are transparent to system operation. NOTE External synchronization is required to achieve meaningful results because there is no internal synchronization between TCLK and the system clock. • PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or CLAMP.
IEEE 1149.1 Test Access Port (JTAG) 31.5.3.8 CLAMP Instruction The CLAMP instruction selects the bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. 31.5.
IEEE 1149.1 Test Access Port (JTAG) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 32 Mechanical Data This chapter contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF528x and MCF521x. 32.1 Pinout Figure 32-1 is the pinout for the MCF5280, MCF5281, and MCF5282. The shaded cells illustrate the differences between the MCF5214 and MCF5216 pinout. NOTE On the MCF5280 device, which does not contain any flash memory, the VSSF and VDDF pins must be connected to VSS and VDD respectively.
Mechanical Data 1 2 3 4 5 6 7 A VSS A15 A16 A18 A21 VPP ETXD3 B A14 A13 A17 A19 VSSF A22 C A12 A11 A10 A20 VDDF D A9 A8 A7 A6 E A5 A4 A3 F A1 A0 G D30 H 8 11 12 13 14 15 16 ETXCLK ERXD3 ERXCLK ECRS VDDF DDATA1 PST2 PST0 VSS ETXD2 ERXER ERXD2 EMDC ECOL VSSF DDATA0 PST1 IRQ7 IRQ6 A23 ETXD1 ERXDV ERXD1 EMDIO VPP DDATA3 PST3 IRQ5 IRQ4 IRQ3 VDDF ETXEN ETXD0 NC ERXD0 ETXER VDDF DDATA2 NC IRQ2 IRQ1 CANRX A2 VSS VDD VDD VD
Mechanical Data Figure 32-2 is the pinout for the MCF5214 and MCF5216. The shaded cells illustrate the differences between the MCF5280, MCF5281, and MCF5282 pinout.
Mechanical Data Table 32-1 lists the MCF521x and MCF528x signals in pin number order for the 256 MAPBGA package. The shaded cells illustrate the difference signals between the two device families. Table 32-1.
Mechanical Data Table 32-1.
Mechanical Data Table 32-1.
Mechanical Data Table 32-1.
Mechanical Data Table 32-1.
Mechanical Data X D M LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA Y 5 K A 0.30 Z A2 A1 256X 4 Z E 0.15 Z DETAIL K ROTATED 90 °CLOCKWISE NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5.
Mechanical Data MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Chapter 33 Electrical Characteristics This chapter contains electrical specification tables and reference timing diagrams for the MCF528x and MCF521x microcontroller units. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. NOTE The parameters specified in this MCU document supersede any values found in the module specifications. 33.1 Maximum Ratings Table 33-1.
Electrical Characteristics 2 3 4 5 6 7 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). Not applicable for MCF5280.
Electrical Characteristics 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Electrical Characteristics Table 33-3. DC Electrical Specifications1 (continued) (VSS = VSSPLL= VSSF = VSSA= 0 VDC) Characteristic Symbol Load Capacitance3 (50% Partial Drive) (100% Full Drive) Min Max Unit pF CL Supply Voltage (includes core modules and pads) RAM Memory Standby Supply Voltage Normal Operation: VDD > VSTBY - 0.3 V Standby Mode: VDD < VSTBY - 0.3 V VDD 25 50 2.7 3.6 0.0 1.8 3.6 3.6 2.7 3.
Electrical Characteristics 250 Idd (mA) 200 Master mode - RUN 150 Master mode - WAIT Single chip - RUN 100 Single chip - WAIT 50 0 8 16 24 32 40 48 56 64 72 80 Frequency (MHz) Figure 33-1. Typical WAIT/DOZE Mode Current Consumption Table 33-5 lists the estimated power consumption for individual modules. The current consumption is for the module itself and does not include power for I/O. Table 33-5.
Electrical Characteristics Table 33-6. Typical Application Power Consumption Application Current 181.6 mA Dhrystone benchmark running from cache and on-chip SRAM (running at 64 MHz fsys) dBUG ROM monitor running from external flash and SDRAM (running at 64 MHz fsys) 155 mA Table 33-7 lists the maximum power consumption specifications. Table 33-7.
Electrical Characteristics 33.5 Phase Lock Loop Electrical Specifications Table 33-8. PLL Electrical Specifications (VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Max Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 Mode System Frequency 1 External Clock Mode On-Chip PLL Frequency Crystal Start-up Time 3, 4 4, 5 80MHz 2 2 33.33 8.33 8.33 66.66 10.0 10.0 80 0 fref / 32 fsys(max) 66.66 66.
Electrical Characteristics 6 7 8 9 10 11 Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to RSTO negating.
Electrical Characteristics Table 33-10. QADC Electrical Specifications (Operating) 1 (VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD = 2.7-3.6V, VSS and VSSA = 0 Vdc, FQCLK = 2.0 MHz, TA within operating temperature range) Parameter Analog Supply — MCF521x Analog Supply — MCF528x VSS Differential Voltage Symbol Min Max Unit VDDA 4.5 3.3 5.5 5.5 V VSS – VSSA -100 100 mV 2 VRL VSSA VSSA + 0.1 V Reference Voltage High 2 VRH VDDA – 0.1 VDDA V VRH – VRL 4.5 3.3 5.5 5.5 V VINDC VSSA–0.
Electrical Characteristics Table 33-11. QADC Conversion Specifications (Operating) (VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD= 2.7-3.6V, VSS and VSSA= 0 Vdc, VRH – VRL = 5 Vdc ± 0.5V, TA within operating temperature range, fsys = 16 MHz) Num Parameter QADC Clock (QCLK) Frequency1 1 Symbol Min Max Unit FQCLK 0.5 2.1 MHz CC 14 28 QCLK cycles TCONV 7.0 14.0 μs TSR — 10 μs 5 — mV -2 2 Counts -3 3 Counts Conversion Cycles 2 3 Conversion Time FQCLK = 2.
Electrical Characteristics Table 33-13. SGFM Flash Module Life Characteristics (VDDF = 2.7 to 3.6 V) Parameter Symbol Value Unit P/E 10,0002 Cycles Retention 10 Years Maximum number of guaranteed program/erase cycles1 before failure Data retention at average operating temperature of 85°C 1 2 A program/erase cycle is defined as switching the bits from 1 → 0 → 1. Reprogramming of a Flash array block prior to erase is not required. 33.
Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. 1.5V CLKOUT(66.67 MHz) TSETUP THOLD Input Setup And Hold Invalid 1.5V Valid 1.5V Invalid trise = 1.5 ns Vh = VIH Input Rise Time Vl = VIL tfall = 1.5 ns Vh = VIH Input Fall Time CLKOUT Vl = VIL B4 B5 Inputs Figure 33-2. General Input Timing Requirements 33.9 Processor Bus Output Timing Specifications Table 33-14 lists processor bus output timings. Table 33-15.
Electrical Characteristics Table 33-15.
Electrical Characteristics S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT B7a B7a CSn A[23:0] SIZ[1:0] TS B6a B6a B8 B8 B8 B9 B9 B9 B8 TIP B9 B8 B6c B0 B7 OE B9 R/W (H) B8 B6b B6b B7 B7 BS[3:0] B11 B4 B12 D[31:0] B5 B13 TA (H) TEA (H) Figure 33-3. Read/Write (Internally Terminated) Timing Figure 33-4 shows a bus cycle terminated by TA showing timings listed in Table 33-15. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Electrical Characteristics S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT CSn B6a B7a B8 B9 A[23:0] SIZ[1:0] B8 TS B9 B8 B9 TIP B6c OE B7 R/W (H) BS[3:0] B6b B7 B5 B4 D[31:0] B2a TA TEA (H) B1a Figure 33-4. Read Bus Cycle Terminated by TA Figure 33-5 shows a bus cycle terminated by TEA; it displays the timings listed in Table 33-15. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Electrical Characteristics S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT CSn B6a B7a B8 B9 A[23:0] SIZ[1:0] B8 B9 TS B8 TIP OE B9 B6c B7 R/W (H) BS[3:0] B6b B7 D[31:0] TA (H) B1a TEA B2a Figure 33-5. Read Bus Cycle Terminated by TEA Figure 33-6 shows an SDRAM read cycle. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Electrical Characteristics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLKOUT D3 D1 A[23:0] Row Column D4 SRAS D2 SCAS 1 D4 DRAMW D5 D[31:0] D6 SDRAM_CS[1:0] D4 BS[3:0] ACTV 1 DACR[CASL] NOP READ NOP PRE =2 Figure 33-6. SDRAM Read Cycle Table 33-16.
Electrical Characteristics Figure 33-7 shows an SDRAM write cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKOUT D3 D1 Row A[23:0] Column SRAS D2 SCAS1 D4 DRAMW D7 D[31:0] D8 SDRAM_CS[1:0] D2 D4 D4 BS[3:0] D4 ACTV 1 NOP WRITE NOP PALL DACR[CASL] = 2 Figure 33-7. SDRAM Write Cycle 33.10 General Purpose I/O Timing Table 33-17. GPIO Timing1, 2 (VDD = 2.7 to 3.
Electrical Characteristics 1 GPIO pins include: Ports A-I, INT, SPI, SCI1/2 (including SCI functions), FlexCAN and Timer. Because of long delays associated with the PQA/PQB pads, signals on the PQA/PQB pins will be updated on the following edge of the clock. 2 CLKOUT G1 G2 G1a G2a GPIO Outputs PQA/PQB Outputs G3 G4 GPIO Inputs G3a G4a PQA/PQB Inputs Figure 33-8. GPIO Timing 33.11 Reset and Configuration Override Timing Table 33-18. Reset and Configuration Override Timing (VDD = 2.7 to 3.
Electrical Characteristics CLKOUT R1 R2 R3 RSTI R4 R4 RSTO R8 R5 R6 R7 Configuration Overrides: (RCON, Override pins) Figure 33-9. RSTI and Configuration Override Timing 33.12 I2C Input/Output Timing Specifications Table 33-19 lists specifications for the I2C input timing parameters shown in Figure 33-10. Table 33-19.
Electrical Characteristics Table 33-20. I2C Output Timing Specifications between SCL and SDA (continued) Num Characteristic Min Max Units I8 1 Start condition setup time (for repeated start condition only) 20 — Bus clocks I9 1 Stop condition setup time 10 — Bus clocks 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 33-20.
Electrical Characteristics Table 33-21. MII Receive Signal Timing Characteristic 1 Num 1 Min Max Unit M1 ERXD[3:0], ERXDV, ERXER to ERXCLK setup 5 — ns M2 ERXCLK to ERXD[3:0], ERXDV, ERXER hold 5 — ns M3 ERXCLK pulse width high 35% 65% ERXCLK period M4 ERXCLK pulse width low 35% 65% ERXCLK period ERXDV, ERXCLK, and ERXD[0] have same timing in 10 Mbps 7-wire interface mode. Figure 33-11 shows MII receive signal timings listed in Table 33-21.
Electrical Characteristics M7 ETXCLK (input) M5 M8 ETXD[3:0] (outputs) ETXEN ETXER M6 Figure 33-12. MII Transmit Signal Timing Diagram 33.13.3 MII Async Inputs Signal Timing (ECRS and ECOL) Table 33-23 lists MII asynchronous inputs signal timing. Table 33-23. MII Async Inputs Signal Timing Num M91 1 Characteristic ECRS, ECOL minimum pulse width Min Max Unit 1.5 — ETXCLK period ECOL has the same timing in 10 Mbit 7-wire interface mode.
Electrical Characteristics M14 M15 EMDC (output) M10 EMDIO (output) M11 EMDIO (input) M12 M13 Figure 33-14. MII Serial Management Channel Timing Diagram 33.14 DMA Timer Module AC Timing Specifications Table 33-25 lists timer module AC timings. Table 33-25.
Electrical Characteristics QS1 QSPI_CS[3:0] QSPI_CLK QS2 QSPI_DOUT QS3 QS4 QS5 QSPI_DIN Figure 33-15. QSPI Timing 33.16 JTAG and Boundary Scan Timing Table 33-27. JTAG and Boundary Scan Timing Characteristics1 Num 1 Symbol Min Max Unit 1 TCLK Frequency of Operation fJCYC DC 1/4 fsys 2 TCLK Cycle Period tJCYC 4 — tCYC 3 TCLK Clock Pulse Width tJCW 25.0 — ns 4 TCLK Rise and Fall Times tJCRF 0.0 3.0 ns 5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 5.
Electrical Characteristics 2 3 3 VIH TCLK (input) 4 VIL 4 Figure 33-16. Test Clock Input Timing TCLK VIL VIH 5 Data Inputs 6 Input Data Valid 7 Data Outputs Output Data Valid 8 Data Outputs 7 Data Outputs Output Data Valid Figure 33-17. Boundary Scan (JTAG) Timing TCLK VIL VIH 9 TDI TMS BKPT 10 Input Data Valid 11 TDO Output Data Valid 12 TDO 11 TDO Output Data Valid Figure 33-18. Test Access Port Timing MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Electrical Characteristics TCLK 14 TRST 13 Figure 33-19. TRST Timing CLKOUT VIL VIH 15 BKPT (Input) B1b 16 B2b Input Data Valid 17 Figure 33-20. BKPT Timing 33.17 Debug AC Timing Specifications Table 33-28 lists specifications for the debug AC timing parameters shown in Figure 33-22. Table 33-28.
Electrical Characteristics CLKOUT D1 D2 PST[3:0] DDATA[3:0] Figure 33-21. Real-Time Trace AC Timing Figure 33-22 shows BDM serial port AC timing for the values in Table 33-28. CLKOUT D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 33-22. BDM Serial Port AC Timing MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Appendix A Register Memory Map Table A-1 summarizes the address, name, and byte assignment for registers within the CPU space. Table A-2 lists an overview of the memory map for the on-chip modules, and Table A-3 is a detailed memory map including all of the registers for on-chip modules. Table A-1.
Register Memory Map Table A-2.
Register Memory Map Table A-2. Module Memory Map Overview (continued) Address Module Size IPSBAR + 0x1C_0000 FlexCAN 64K IPSBAR + 0x1D_0000 CFM (Flash) Control Registers 64K IPSBAR + 0x400_0000 CFM (Flash) Memory for IPS Reads and Writes 512K Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map Table A-3.
Register Memory Map MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Appendix B Revision History This appendix lists major changes between versions of the MCF5282UM document. B.1 Changes Between Rev. 0 and Rev. 0.1 Table B-1. Rev. 0 to Rev. 0.1 Changes Location Description Title page Changed title from “MCF5282 ColdFire® Integrated Microprocessor User’s Manual” to “MCF5282 ColdFire® Microcontroller User’s Manual.” 33.1/33-1 Added “This product incorporates SuperFlash® technology licensed from SST.
Revision History Table B-1. Rev. 0 to Rev. 0.1 Changes (continued) Location Description Figure 32-1 on page 32-2 Changed “RAS0” and “RAS1” to “SDRAM_CS0” and “SDRAM_CS1.” Table 32-1 on page 32-4 Added Table 32-1. Table 33-3 on page 33-3 Changed max input high voltage to 5.25 V. Appendix A, Changed “System Integration Module” to “System Control Module.” “Register Memory Map B.2 Changes Between Rev. 0.1 and Rev. 1 Table B-2. Rev. 0.1 to Rev.
Revision History Table B-2. Rev. 0.1 to Rev. 1 Changes (continued) Location Description Chapter 8, “System Moved information in Section 8.4.6, “DMA Request Control Register,” to Section 16.2, “DMA Request Control Module Control (DMAREQC).” (SCM) and 16.2/16-2 Figure 8-2 on page Changed offset for the copy of RAMBAR to “0x008.” 8-4 Table 8-5 on page 8-6 8.5.2.1/8-9 Changed CWTIC to CWTIF.
Revision History Table B-2. Rev. 0.1 to Rev. 1 Changes (continued) Location Description Table 25-12 on page Changed equation in PRES_DIV field description to the following: 25-22 f SYS S-clock = -------------------------------------------2 ( PRESDIV + 1 ) 27.6.2/27-8 Added “Note: When Flash security is enabled, the chip will boot in single chip mode regardless of the external reset configuration.
Revision History Table B-2. Rev. 0.1 to Rev. 1 Changes (continued) Location 33.13/33-21 Description Added timing diagrams and tables to Section 33.13, “Fast Ethernet AC Timing Specifications.” Table 33-27 on page Changed the max value in spec 1 to “1/4.” 33-25 Table 33-27 on page Changed the min value in spec 2 to “4.” 33-25 Table 33-27 on page Changed the min value in spec 3 to “25.” 33-25 Table 33-27 on page Changed the min value in spec 6 to “25.
Revision History Table B-3. Rev. 1 to Rev. 2 Changes (continued) Location Description Table 8-3/8-5 Add the following note to the BDE bit description: “The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to the SRAM. For more information, see Section 5.3.1, ‘SRAM Base Address Register (RAMBAR).’” Figure 9-1/9-3 Remove ÷ 2 from CLKGEN block. 10.3.6/10-11 10.5/10-17 Figure 12-4/12-8 13.
Revision History B.4 Changes Between Rev. 2 and Rev. 2.1 Table B-4. Rev. 2 to Rev. 2.1 Changes Location Title Page Table 33-8/33-9 B.5 Description Added MCF5280 to “Devices Supported” list on the title page. Deleted reference to “TA=TL to TH” Changes Between Rev. 2.1 and Rev. 2.2 Table B-5. Rev. 2.1 to Rev. 2.2 Changes Location Chapter 33 B.6 Description Added Power Spec info to Electricals chapter Changes Between Rev. 2.2 and Rev. 2.3 Table B-6. Rev. 2.2 to Rev. 2.
Revision History Table B-6. Rev. 2.2 to Rev. 2.3 Changes (continued) Location Description Table 25-19/25-32 Changed BUFnI field description from “To clear an interrupt flag, first read the flag as a one, then write it as a zero” to “To clear an interrupt flag, first read the flag as a one, then write it as a one.” Chapter 33 B.7 Updated power consumption tables. Changes Between Rev. 2.3 and Rev. 3 Table B-7. Rev. 2.3 to Rev.
Revision History Table B-7. Rev. 2.3 to Rev. 3 Changes (continued) Location Chapter 8 Description Remove any references to the core watchdog timer being able to reset the device. It is only able to interrupt the processor. Use the peripheral watchdog timer described in Chapter 18 if needing a watchdog timer to reset the device. Table 8-5/Page 8-6 CWCR[CWRI] bit description, change “...is programmed in the interrupt control register 7 (ICR7)...” to “...
Revision History Table B-7. Rev. 2.3 to Rev. 3 Changes (continued) Location Description Section 17.4.6/Page 17-7 Add the following subsection entitled “Duplicate Frame Transmission”: The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being processed internally (as a result of a wrap).
Revision History Table B-7. Rev. 2.3 to Rev. 3 Changes (continued) Location Description Table 26-1/Page 26-5 Change description field for DTOUT1 from “DMA timer 1 output / Port TD[3]...” to “DMA timer 1 output / Port TD[2]...” Change description field for DTIN0 from “DMA timer 0 input / Port TD[3]...” to “DMA timer 1 output / Port TD[1]...” Change description field for DTOUT0 from “DMA timer 0 output / Port TD[3]...” to “DMA timer 1 output / Port TD[0]...
Revision History Table B-7. Rev. 2.3 to Rev. 3 Changes (continued) Location Description Section 33.13.2/Page 33-22 Remove second sentence: “There is no minimum frequency requirement.” Remove second paragraph as this feature is not supported on this device: “The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Appendix C Index A A/D converter bias 28-34 block diagram 28-32 channel decode 28-33 comparator 28-33 cycle times 28-32 multiplexer 28-33 operation 28-31 sample buffer 28-33 state machine 28-34 successive approximation register (SAR) 28-34 Acknowledge error (ACKERR) 25-26 Address variant 30-4 Analog inputs 28-66 Analog power signals 28-56 Analog reference signals 28-56 Analog supply filtering 28-61 grounding 28-61 Async inputs signal timing 33-23 B BDM see debug commands DUMP 30-27 FILL 30-29 format 30-20 G
SACU 8-11 Bus off interrupt (BOFFINT) 25-27 BUSY 25-11 BYPASS instruction 31-9 C Cache block diagram 4-2 coherency 4-8 fill buffer 4-2, 4-9 invalidation 4-8 miss fetch algorithm 4-9 organization 4-1 registers access control 0–1 (ACRn) 2-7, 4-6 control (CACR) 2-7, 4-3 SRAM interaction 4-7 Channel flags 20-21 Chip configuration module block diagram 27-2 boot device selection 27-9 chip mode selection 27-8 chip select 27-10 clock mode selection 27-9 features 27-1 interrupts 27-10 memory map 27-3 operation low-p
reads 6-17 setting CFMCLKD 6-17 stop mode 6-21 verify 6-18 writes 6-17 registers clock divider (CFMCLKD) 6-9 setting 6-17 command (CFMCMD) 6-16 configuration (CFMCR) 6-8 data access (CFMDACC) 6-14 FLASHBAR 6-5 protection (CFMPROT) 6-12 security (CFMSEC) 6-10 supervisor access (CFMSACC) 6-13 user status (CFMUSTAT) 6-15 reset 6-23 security back door access 6-23 erase verify check 6-23 Collision handling 17-42 Core block diagram 2-1 low-power modes 7-6 registers address (An) 2-4 condition code (CCR) 2-6 data (
I2C input/output timing specifications 33-20 I2C output timing between SCL and SDA 33-20 JTAG and boundary scan timing 33-25 maximum ratings 33-1 MII async inputs signal timing 33-23 MII receive signal timing 33-21 MII serial management channel timing 33-23 MII transmit signal timing 33-22 PLL specifications 33-4 QADC absolute maximum ratings 33-8 QADC operating conversion specifications 33-10 QADC operating electrical specifications 33-9 QSPI AC timing specifications 33-24 QSPI specifications 33-24 reset a
Exceptions access error 2-18 divide-by-zero 2-20 exception stack frame 2-17 format error 2-21 illegal instruction 2-19 overview 2-15 privilege violation 2-20 reset 2-22 trace 2-20 TRAP instruction 2-22 External interface module (EIM), seebus EXTEST instruction 31-7 F Fault confinement state (FCS) 25-27 Fault-on-fault 2-22 Fault-on-fault halt 30-17 FEC, see Ethernet Flash, see ColdFire Flash module FlexCAN bit timing 25-12 CAN system overview 25-4 error counters 25-13 features 25-1 format frames 25-5–25-7 ID
gated time accumulation 20-19 registers channel (GPTCn) 20-13 compare force (GPCFORC) 20-6 control 1–2 (GPTCTLn) 20-9 counter (GPTCNT) 20-7 flag 1–2 (GPTFLGn) 20-12 input capture/output compare select (GPTIOS) 20-5 interrupt enable (GPTIE) 20-10 output compare 3 data (GPTOC3D) 20-7 output compare 3 mask (GPTOC3M) 20-6 port data (PORTTn) 20-16 port data direction (GPTDDR) 20-17 pulse accumulator control (GPTPACTL) 20-14 pulse accumulator counter (GPTPACNT) 20-16 pulse accumulator flag (GPTPAFLG) 20-15 system
interrupts ColdFire Flash module 6-23 debug 2-21, 30-37 FlexCAN 25-17 overview 10-1 PIT 19-7 prioritization 10-4 QADC operation 28-68 sources 28-68 recognition 10-3 sources 10-13 vector determination 10-4 memory map 10-4 operation general 10-2 low-power modes 7-9 registers (IACKLPRn) 10-11 interrupt control (ICRnx) 10-12 interrupt force high/low (INTFRCHn, INTFRCLn) 10-9 interrupt pending high/low (IPRHn, IPRLn) 10-6 interrupt request level (IRLRn) 10-11 mask high/low (IMRHn, n) 10-7 J JTAG block diagram 31
ColdFire Flash module 6-4, 6-7 EMAC 3-3 EPORT 11-3 FlexCAN 25-2 general purpose timers 20-4 GPIO 26-7 I2C 24-3 interrupt controller 10-4 JTAG 31-4 PIT 19-2 power management 7-2 QADC 28-6 QSPI 22-3 reset controller 29-2 SCM 8-2, 8-12 SDRAM controller 15-4 UART modules 23-3 watchdog timer 18-2 Message buffers extended format frames 25-5, 25-7 handling 25-10 overload frames 25-12 receive codes 25-6 deactivation 25-10 error status flag (RXWARN) 25-27 pin configuration control (RXMODE) 25-20 remote frames 25-11
low-power control (LPCR) 7-4 low-power interrupt control (LPICR) 7-2 Prescaler divide (PRESDIV) bits 25-22 Processor status 30-2, 30-39 Program counter 2-7 Programmable interrupt timers operation low-power modes 7-10 Programming model chip configuration module 27-3 debug 30-5 EPORT 7-1 power management 7-1 Pulse accumulator event counter mode 20-18 gated time accumulation 20-19 input interrupt 20-22 overflow interrupt 20-22 PULSE instruction 30-3 Q QADC A/D converter bias 28-34 block diagram 28-32 channel d
model 22-11 receive 22-11 transmit 22-12 registers address (QAR) 22-7 command RAM (QCRn) 22-8 data (QDR) 22-8 delay (QDLYR) 22-5 interrupt (QIR) 22-6 mode (QMR) 22-3 wrap (QWR) 22-6 Rx RAM 22-11 signals 22-2 timing diagram 33-25 Tx delays 22-13 length 22-14 RAM 22-12 R Registers cache access control 0–1 (ACRn) 2-7, 4-6 control (CACR) 2-7, 4-3 chip configuration module chip configuration (CCR) 27-4 chip identification (CIR) 27-6 reset configuration (RCON) 27-5 chip select module address (CSARn) 12-6 control
error and status (ESTAT) 25-25 free running timer (TIMER) 25-23 interrupt flag (IFLAG) 25-28 interrupt mask (IMASK) 25-27 module configuration (CANMCR) 25-18 prescaler divide (PRESDIV) 25-22 receive error counter (RXECTR) 25-29 receive mask (RXGMASK, RXnMASK) 25-24 transmit error counter (TXECTR) 25-30 general purpose timers channel (GPTCn) 20-13 compare force (GPCFORC) 20-6 control 1–2 (GPTCTLn) 20-9 counter (GPTCNT) 20-7 flag 1–2 (GPTFLGn) 20-12 input capture/output compare select (GPTIOS) 20-5 interrupt
initialization 15-23 settings 15-18 timers DTIM capture (DTCRn) 21-7 counters (DTCNn) 21-8 event (DTERn) 21-5 mode (DTMRn) 21-3 reference (DTRRn) 21-7 PIT control and status (PCSR) 19-3 count (PCNTR) 19-5 modulus (PMR) 19-5 UART modules auxiliary control (UACRn) 23-13 baud rate generator (UBG1n/UBG2n) 23-15 clock select (UCSRn) 23-9 command (UCRn) 23-9 input port (UIPn) 23-15 input port change (UIPCRn) 23-12 interrupt status/mask (UISRn/UIMRn) 23-13 mode 1 (UMR1n) 23-5 mode 2 (UMRn) 23-6 output port command
address multiplexing 15-9 general guidelines 15-9 overview 15-1 registers address and control 1–0 (DACRn) 15-6 control (DCR) 15-4 mask (DMRn) 15-8 mode register initialization 15-23 settings 15-18 self-refresh 15-16 timing diagrams read cycle 33-17 write cycle 33-18 timing specifications 33-17 Self-received frames 25-10 Signals block diagram 14-2 bus address bus (A23–0) 14-19 byte strobes (BS3–0) 14-19 chip select (CS6–0) 14-21 data (D31–0) 14-19 output enable (OE) 14-19 read/write (R/W) 14-20 summary 13-1
test data input/development serial input (TDI/DSI) 31-3 test data output/development serial output (TDO/DSO) 31-4 test mode select/breakpoint (TMS/BKPT) 31-3 test reset/development serial clock (TRST/DSCLK) 31-3 overview 14-1 power and reference VDD 14-32 VDDA, VSSA 14-32 VDDF, VSSF 14-32 VDDH 14-32 VDDPLL, VSSPLL 14-32 VPP 14-32 VRH, VRL 14-32 VSS 14-32 VSTBY 14-32 QADC analog input (ANn/ANx) 14-28–14-29 analog power (VDDA, VSSA) 28-56 analog reference (VRH, VRL) 28-56 dedicated digital I/O port supply (VD
set-and-forget 19-6 registers control and status (PCSR) 19-3 count (PCNTR) 19-5 modulus (PMR) 19-5 timeout 19-7 watchdog, see watchdog timer 18-2 Timing diagrams debug BDM serial port AC timing 33-28 real-time trace AC timing 33-28 Ethernet MII async input signal 33-23 general input timing requirements 33-12 GPIO 33-19 digital input 26-28 digital output 26-28 I2C input/output timing 33-21 JTAG BKPT timing 33-27 boundary scan 33-26 test access port 33-26 test clock input timing 33-26 TRST timing 33-27 QADC b
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev.
Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules DMA Timers Queued Serial
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B IND Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Pro
