Datasheet

IEEE 1149.1 Test Access Port (JTAG)
31-6 Freescale Semiconductor
31.5.2 TAP Controller
The TAP controller is a state machine that changes state based on the sequence of logical values on the
TMS pin. Figure 31-3 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCLK signal.
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As
Figure 31-3 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also
causes the state machine to enter the test-logic-reset state, whatever the initial state.
Figure 31-3. TAP Controller State Machine Flow
31.5.3 JTAG Instructions
Table 31-5 describes public and private instructions.
RUN-TEST/IDLE
TEST-LOGIC-RESET
1
1
SELECT DR-SCAN
CAPTURE-DR
EXIT1-DR
PAUSE-DR
UPDATE-DR
SELECT IR-SCAN
SHIFT-DR
EXIT2-DR
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
0
0
1
1
0
0
0
1
1
10
0
0
1
1
0
0
1
1
0
1
0
1
10
1
1
0
0
1
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3