Datasheet

I
2
C Interface
Freescale Semiconductor 24-3
24.2 Memory Map/Register Definition
The below table lists the configuration registers used in the I
2
C interface.
24.2.1 I
2
C Address Register (I2ADR)
I2ADR holds the address the I
2
C responds to when addressed as a slave. It is not the address sent on the
bus during the address transfer when the module is performing a master transfer.
24.2.2 I
2
C Frequency Divider Register (I2FDR)
The I2FDR, shown in Figure 24-3, provides a programmable prescaler to configure the I
2
C clock for
bit-rate selection.
Table 24-1. I
2
C Module Memory Map
IPSBAR
Offset
Register Access Reset Value Section/Page
0x00_0300 I
2
C Address Register (I2ADR) R/W 0x00 24.2.1/24-3
0x00_0304 I
2
C Frequency Divider Register (I2FDR) R/W 0x00 24.2.2/24-3
0x00_0308 I
2
C Control Register (I2CR) R/W 0x00 24.2.3/24-4
0x00_030C I
2
C Status Register (I2SR) R/W 0x81 24.2.4/24-5
0x00_0310 I
2
C Data I/O Register (I2DR) R/W 0x00 24.2.5/24-6
IPSBAR
Offset:
0x00_0300 (I2ADR) Access: User read/write
76543210
R
ADR
0
W
Reset:00000000
Figure 24-2. I
2
C Address Register (I2ADR)
Table 24-2. I2ADR Field Descriptions
Field Description
7–1
ADR
Slave address. Contains the specific slave address to be used by the I
2
C module. Slave mode is the default I
2
C mode
for an address match on the bus.
0 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3