Datasheet

Electrical Characteristics
MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 41
Figure 28. Test Clock Input Timing
Figure 29. Boundary Scan (JTAG) Timing
J9 TMS, TDI Input Data Setup Time to TCLK Rise t
TAPBST
4—ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise t
TAPBHT
10 — ns
J11 TCLK Low to TDO Data Valid t
TDODV
026ns
J12 TCLK Low to TDO High Z t
TDODZ
08ns
J13 TRST
Assert Time t
TRSTAT
100 — ns
J14 TRST
Setup Time (Negation) to TCLK High t
TRSTST
10 — ns
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
Table 33. JTAG and Boundary Scan Timing (continued)
Num Characteristic
1
Symbol Min Max Unit
TCLK
V
IL
V
IH
J4
J4
(input)
J2
J3 J3
Input Data Valid
Output Data Valid
Output Data Valid
TCLK
Data Inputs
Data Outputs
Data Outputs
Data Outputs
V
IL
V
IH
J7
J8
J7
J6J5