Datasheet

Signal Descriptions
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 5
External Interrupts Port
5
IRQ7
2
PIRQ7
2
— — I
EVDD
134 A5 142 C7
IRQ4
2
PIRQ4
2
DREQ0
2
— I
EVDD
133 C6 141 D7
IRQ1
2
PIRQ1
2
— — I
EVDD
132 B6 140 D8
FEC
FEC_MDC PFECI2C3 I2C_SCL
2
U2TXD O
EVDD
— — 148 D6
FEC_MDIO PFECI2C2 I2C_SDA
2
U2RXD I/O
EVDD
— — 147 C6
FEC_TXCLK PFECH7 — — I
EVDD
— — 157 B3
— PFECH6 — U1RTS O
EVDD
142 A2 — —
FEC_TXEN PFECH6 — U1RTS O
EVDD
— — 158 A2
FEC_TXD0 PFECH5 — — O
EVDD
— — 3 B1
FEC_COL PFECH4 — — I
EVDD
— — 7 D3
FEC_RXCLK PFECH3 — — I
EVDD
— — 154 B4
FEC_RXDV PFECH2 — — I
EVDD
— — 153 A4
FEC_RXD0 PFECH1 — — I
EVDD
— — 152 D5
FEC_CRS PFECH0 — — I
EVDD
— — 8 D2
FEC_TXD[3:1] PFECL[7:5] — — O
EVDD
— — 6–4 C1, C2, B2
— PFECL4 — U0RTS O
EVDD
141 D5 — —
FEC_TXER PFECL4 — U0RTS O
EVDD
— — 156 A3
FEC_RXD[3:2] PFECL[3:2] — — I
EVDD
— — 149–150 A5, B5
— PFECL1 — U1CTS I
EVDD
139 B4 — —
FEC_RXD1 PFECL1 — U1CTS I
EVDD
— — 151 C5
— PFECL0 — U0CTS I
EVDD
140 E4 — —
FEC_RXER PFECL0 — U0CTS I
EVDD
— — 155 C4
Note: The MCF5207 does not contain an FEC module. However, the UART0 and UART1 control signals (as well as their GPIO signals)
are available by setting the appropriate FEC GPIO port registers.
I
2
C
I2C_SDA
2
PFECI2C0
2
U2RXD
2
— I/O
EVDD
— — —D1
I2C_SCL
2
PFECI2C1
2
U2TXD
2
— I/O
EVDD
— — —E4
DMA
DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing:
TS
and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0.
Table 3. MCF5207/8 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Dir.
1
Voltage
Domain
MCF5207
144
LQFP
MCF5207
144
MAPBGA
MCF5208
160
QFP
MCF5208
196
MAPBGA