Datasheet

MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor40
5.15 JTAG and Boundary Scan Timing
Figure 28. Test Clock Input Timing
Table 24. JTAG and Boundary Scan Timing
Num Characteristics
1
NOTES:
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
Symbol Min Max Unit
J1 TCLK Frequency of Operation f
JCYC
DC 1/4 f
sys/2
J2 TCLK Cycle Period t
JCYC
4—t
CYC
J3 TCLK Clock Pulse Width t
JCW
26 — ns
J4 TCLK Rise and Fall Times t
JCRF
03 ns
J5 Boundary Scan Input Data Setup Time to TCLK Rise t
BSDST
4— ns
J6 Boundary Scan Input Data Hold Time after TCLK Rise t
BSDHT
26 — ns
J7 TCLK Low to Boundary Scan Output Data Valid t
BSDV
033 ns
J8 TCLK Low to Boundary Scan Output High Z t
BSDZ
033 ns
J9 TMS, TDI Input Data Setup Time to TCLK Rise t
TAPBST
4— ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise t
TAPBHT
10 — ns
J11 TCLK Low to TDO Data Valid t
TDODV
026 ns
J12 TCLK Low to TDO High Z t
TDODZ
08 ns
J13 TRST
Assert Time t
TRSTAT
100 — ns
J14 TRST
Setup Time (Negation) to TCLK High t
TRSTST
10 — ns
TCLK
V
IL
V
IH
J3 J3
J4 J4
J2
(input)