Datasheet

Electrical Characteristics
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 37
5.12.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,
FEC_TXER, FEC_TXCLK)
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. In
addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency.
Figure 24 shows MII transmit signal timings listed in Table 19.
Figure 24. MII Transmit Signal Timing Diagram
5.12.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 20 lists MII asynchronous inputs signal timing.
Figure 25 shows MII asynchronous input timings listed in Table 20.
Figure 25. MII Async Inputs Timing Diagram
Table 19. MII Transmit Signal Timing
Num Characteristic Min Max Unit
M5 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER
invalid
5— ns
M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid — 25 ns
M7 FEC_TXCLK pulse width high 35% 65% FEC_TXCLK period
M8 FEC_TXCLK pulse width low 35% 65% FEC_TXCLK period
Table 20. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 FEC_CRS, FEC_COL minimum pulse width 1.5 — FEC_TXCLK period
M6
FEC_TXCLK (input)
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M5
M7
M8
FEC_CRS
M9
FEC_COL