Datasheet

MCF5208 ColdFire

Microprocessor Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor36

Figure 22. I

C Input/Output Timings

5.12 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.

5.12.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_RXCLK frequency.

Table 18 lists MII receive channel timings.

Figure 23 shows MII receive signal timings listed in Table 18.

Figure 23. MII Receive Signal Timing Diagram

Table 18. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK

setup

5— ns

M2 FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold 5 — ns

M3 FEC_RXCLK pulse width high 35% 65% FEC_RXCLK period

M4 FEC_RXCLK pulse width low 35% 65% FEC_RXCLK period

I2 I6

I1 I4

I8 I9

I2C_SCL

I2C_SDA

M1 M2

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER