Datasheet

Electrical Characteristics
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 29
5.8.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The SDRAM controller is a DDR controller with an SDR mode. Because it is designed to support
DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The ColdFire
processor accomplishes this by asserting a signal called SD_SDR_DQS during read cycles. Take care
during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS
signal and its usage.
Table 12. SDR Timing Specifications
Symbol Characteristic Symbol Min Max Unit Notes
Frequency of Operation 60 83.33 MHz
1
NOTES:
1
The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the
PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate.
SD1 Clock Period (t
CK
)t
SDCK
12 16.67 ns
2
2
SD_CLK is one SDRAM clock in (ns).
SD3 Pulse Width High (t
CKH
)t
SDCKH
0.45 0.55 SD_CLK
3
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD4 Pulse Width Low (t
CKL
)t
SDCKL
0.45 0.55 SD_CLK
3
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Valid (t
CMV
)
t
SDCHACV
—0.5× SD_CLK
+1.0
ns
SD6 Address, SD_CKE, SD_CAS
, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Hold (t
CMH
)
t
SDCHACI
2.0 — ns
SD7 SD_SDR_DQS Output Valid (t
DQSOV
)t
DQSOV
—Self timedns
4
4
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from
this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SD8 SD_DQS[3:2] input setup relative to SD_CLK (t
DQSIS
)t
DQVSDCH
0.25 × SD_CLK 0.40 × SD_CLK ns
5
5
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SD9 SD_DQS[3:2] input hold relative to SD_CLK (t
DQSIH
)t
DQISDCH
Does not apply. 0.5 SD_CLK fixed width.
6
6
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
SD10 Data (D[31:0]) Input Setup relative to SD_CLK
(reference only) (t
DIS
)
t
DVSDCH
0.25 × SD_CLK — ns
7
7
Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec
is provided as guidance.
SD11 Data Input Hold relative to SD_CLK (reference only)
(t
DIH
)
t
DISDCH
1.0 — ns
SD12 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output
Valid (t
DV
)
t
SDCHDMV
—0.75× SD_CLK
+ 0.5
ns
SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output
Hold (t
DH
)
t
SDCHDMI
1.5 — ns