Datasheet

MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor28
Figure 14. FlexBus Read Timing
Figure 15. Flexbus Write Timing
5.8 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The
SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for
Class I or Class II drive strength.
FB_CLK
FB_R/W
S0 S1 S2 S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWE
n
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2 FB5
FB4
FB7
FB6
FB_CLK
FB_R/W
FB_TS
FB_OE
S0 S2 S3
DATA
S1
ADDR[31:X]
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
FB_CSn, FB_BE/BWEn
FB_TA
FB3
FB1
FB2
FB7
FB6