Datasheet

Electrical Characteristics
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 27
5.7.1.1 FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
Table 11. FlexBus AC Timing Specifications
Num Characteristic Symbol Min Max Unit Notes
Frequency of Operation 83.33 Mhz f
sys/2
FB1 Clock Period (FB_CLK) t
FBCK
12 ns t
cyc
FB2 Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
t
FBCHDCV
—7.0 ns
1
NOTES:
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8, “SDRAM Bus” for SD_CS[1:0]
timing.
FB3 Data, and Control Output Hold ((A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
t
FBCHDCI
1— ns
1, 2
2
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for
more information.
FB4 Data Input Setup t
DVFBCH
3.5 — ns
FB5 Data Input Hold t
DIFBCH
0— ns
FB6 Transfer Acknowledge (T
A) Input Setup t
CVFBCH
4— ns
FB7 Transfer Acknowledge (T
A) Input Hold t
CIFBCH
0— ns