Datasheet

Electrical Characteristics
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 25
5.7 External Interface Timing Characteristics
Table 11 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.
9 XTAL Current I
XTAL
13mA
10 Total on-chip stray capacitance on XTAL C
S_XTAL
1.5 pF
11 Total on-chip stray capacitance on EXTAL C
S_EXTAL
1.5 pF
12 Crystal capacitive load C
L
See crystal
spec
13 Discrete load capacitance for XTAL C
L_XTAL
2*C
L
-
C
S_XTAL
-
C
PCB_XTAL
7
pF
14 Discrete load capacitance for EXTAL C
L_EXTAL
2*C
L
-
C
S_EXTAL
-
C
PCB_EXTAL
7
pF
17 CLKOUT Period Jitter,
3, 4, 7, 8, 9
Measured at f
SYS
Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
C
jitter
—
—
10
TBD
% f
sys/2
% f
sys/2
18 Frequency Modulation Range Limit
3, 10, 11
(f
sys
Max must not be exceeded)
C
mod
0.8 2.2 %f
sys/2
19 VCO Frequency. f
vco
= (f
ref *
PFD)/4 f
vco
350 540 MHz
NOTES:
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24 MHz. For higher input clock
frequencies, the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2
All internal registers retain data at 0 Hz.
3
This parameter is guaranteed by characterization before qualification rather than 100% tested.
4
Proper PC board layout procedures must be followed to achieve specifications.
5
This parameter is guaranteed by design rather than 100% tested.
6
This specification is the PLL lock time only and does not include oscillator start-up time.
7
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL V
DD
, EV
DD
, and V
SS
and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10
Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz.
11
Modulation range determined by hardware design.
Table 10. PLL Electrical Characteristics (continued)
Num Characteristic Symbol
Min.
Value
Max.
Value
Unit