Datasheet
Electrical Characteristics
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor 21
5.4.1 PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V
DD
pins.
The filter shown in Figure 11 should be connected between the board V
DD
and the PLLV
DD
pins. The
resistor and capacitors should be placed as close to the dedicated PLLV
DD
pin as possible.
Figure 11. System PLL V
DD
Power Filter
5.4.2 Supply Voltage Sequencing and Separation Cautions
The relationship between SDV
DD
and EV
DD
is non-critical during power-up and power-down sequences.
SDV
DD
(2.5V or 3.3V) and EV
DD
are specified relative to IV
DD
.
5.4.2.1 Power Up Sequence
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, the sense circuits in the I/O pads cause all pad output
drivers connected to the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after
EV
DD
/SDV
DD
powers up before IV
DD
must power up. IV
DD
should not lead the EV
DD
, SDV
DD
, or
PLLV
DD
by more than 0.4 V during power ramp-up or there will be high current in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on
the internal ESD protection clamp diodes.
5.4.2.2 Power Down Sequence
If IV
DD
/PLLV
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a
high impedance state. There is no limit on how long after IV
DD
and PLLV
DD
power down before EV
DD
or SDV
DD
must power down. IV
DD
should not lag EV
DD
, SDV
DD
, or PLLV
DD
going low by more than
Weak Internal Pull Up Device Current, tested at V
IL
Max.
1
I
APU
-10 - 130 μA
Input Capacitance
2
All input-only pins
All input/output (three-state) pins
C
in
—
—
7
7
pF
NOTES:
1
Refer to the signals section for pins having weak internal pull-up devices.
2
This parameter is characterized before qualification rather than 100% tested.
Table 7. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
Board V
DD
10 Ω
0.1 µF
PLL V
DD
Pin
10 µF
GND