Freescale Semiconductor Data Sheet: Technical Data MCF5208EC Rev. 3, 9/2009 MCF5208 ColdFire® Microprocessor Data Sheet Supports MCF5207 & MCF5208 by: Microcontroller Solutions Group The MCF5207 and MCF5208 devices are highly-integrated, 32-bit microprocessors based on the version 2 ColdFire microarchitecture.
MCF5207/8 Device Configurations 1 MCF5207/8 Device Configurations The following table compares the two devices described in this document: Table 1. MCF5207 & MCF5208 Configurations Module MCF5207 MCF5208 Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) • • Core (System) Clock up to 166.67 MHz Peripheral and External Bus Clock (Core clock ÷ 2) up to 83.33 MHz Performance (Dhrystone/2.
Signal Descriptions 3 Signal Descriptions The following table lists all the MCF5208 pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts” for package diagrams. For a more detailed discussion of the MCF5208 signals, consult the MCF5208 Reference Manual (MCF5208RM). NOTE In this table and throughout this document, a single signal within a group is designated without square brackets (i.e.
Signal Descriptions Dir.1 Voltage Domain Table 3.
Signal Descriptions GPIO Alternate 1 Alternate 2 Voltage Domain Signal Name Dir.1 Table 3.
Signal Descriptions GPIO MCF5207 144 LQFP U2RTS O EVDD 126 A8 132 D10 2 — O EVDD 127 C7 133 A9 2 Alternate 1 Alternate 2 Dir.1 Signal Name Voltage Domain Table 3.
Signal Descriptions GPIO Alternate 1 Alternate 2 ALLPST — — — Voltage Domain Signal Name Dir.1 Table 3.
Mechanicals and Pinouts 4 Mechanicals and Pinouts Drawings in this section show the pinout and the packaging and mechanical characteristics of the MCF5207 and MCF5208 devices. NOTE The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. 4.
Mechanicals and Pinouts 4.2 Package Dimensions—144 LQFP Figure 2 and Figure 3 show MCF5207CAB166 package dimensions. Figure 2. MCF5207CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Mechanicals and Pinouts View A Section A-A Rotated 90× CW 144 Places View B Figure 3. MCF5207CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Mechanicals and Pinouts 4.3 Pinout—144 MAPBGA The pinout of the MCF5207CVM166 device is shown below.
Mechanicals and Pinouts 4.4 Package Dimensions—144 MAPBGA Figure 5 shows the MCF5207CAB166 package dimensions. Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA) MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Mechanicals and Pinouts 4.
Mechanicals and Pinouts 4.6 Package Dimensions—160 QFP The package dimensions of the MCF5208CAB166 device are shown in the figures below. Top View Figure 7. MCF5208CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Mechanicals and Pinouts SECTION B-B DETAIL A Figure 8. MCF5208CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Mechanicals and Pinouts 4.7 Pinout—196 MAPBGA Figure 9 shows a pinout of the MCF5208CVM166 device.
Electrical Characteristics 4.8 Package Dimensions—196 MAPBGA The package dimensions for the MCF5208CVM166 device is shown below. Top View Bottom View Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA) 5 Electrical Characteristics 5.1 Maximum Ratings Table 4. Absolute Maximum Ratings1, 2 Rating Symbol Value Unit Core Supply Voltage IVDD – 0.5 to +2.0 V CMOS Pad Supply Voltage EVDD – 0.3 to +4.0 V DDR/Memory Pad Supply Voltage SDVDD – 0.3 to +4.
Electrical Characteristics Table 4. Absolute Maximum Ratings1, 2 (continued) Operating Temperature Range (Packaged) TA (TL - TH) – 40 to 85 °C Tstg – 55 to 150 °C Storage Temperature Range NOTES: 1 Functional operating conditions are given in Section 5.4, “DC Electrical Specifications”. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device.
Electrical Characteristics 3 4 5 6 7 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
Electrical Characteristics 2 5.4 A device is defined as a failure if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. DC Electrical Specifications Table 7. DC Electrical Specifications Characteristic Symbol Min Max Unit Core Supply Voltage IVDD 1.4 1.
Electrical Characteristics Table 7. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit Weak Internal Pull Up Device Current, tested at VIL Max.1 IAPU -10 - 130 μA Input Capacitance 2 All input-only pins All input/output (three-state) pins Cin — — 7 7 pF NOTES: 1 Refer to the signals section for pins having weak internal pull-up devices. 2 This parameter is characterized before qualification rather than 100% tested. 5.4.
Electrical Characteristics 0.4 V during power down or there is an undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is: 1. Drop IVDD/PLLVDD to 0 V. 2. Drop EVDD/SDVDD supplies. 5.5 Current Consumption All of the below current consumption data is lab data measured on a single device using an evaluation board.
Electrical Characteristics 5 See the description of the low-power control register (LCPR) in the MCF5208 Reference Manual for more information on stop modes 0–3. The figure below illustrates the power consumption in a graphical format. Power Consumption (mW) 250 Stop 0 - Flash 200 Stop 1 - Flash Stop 2 - Flash 150 Stop 3 - Flash Wait/Doze - Flash 100 Run - Flash 50 0 44 48 56 64 72 83.33 83.33(peak) fsys/2 (MHz) Figure 12. Current Consumption in Low-Power Modes Table 9.
Electrical Characteristics Table 9. Typical Active Current Consumption Specifications1 (continued) fsys/2 Frequency Voltage (V) 56 MHz 64 MHz 72 MHz 83.33 MHz Typical2 Active (mA) Peak3 Active (mA) SRAM Flash 3.3 10.09 30.71 38.97 2.5 16.43 20.71 17.65 1.5 30.07 35.90 47.90 3.3 15.72 31.37 42.10 2.5 16.56 21.08 17.95 1.5 32.19 38.72 53.50 3.3 20.97 31.40 48.80 2.5 16.87 21.70 18.20 1.5 35.90 43.20 59.50 3.3 31.37 25.83 48.60 2.5 17.21 22.80 18.83 1.
Electrical Characteristics Table 10. PLL Electrical Characteristics (continued) Num Characteristic Symbol Min. Value Max. Value Unit IXTAL 1 3 mA 9 XTAL Current 10 Total on-chip stray capacitance on XTAL CS_XTAL 1.5 pF 11 Total on-chip stray capacitance on EXTAL CS_EXTAL 1.
Electrical Characteristics All other timing relationships can be derived from these values. Timings listed in Table 11 are shown in Figure 14 and Figure 15. * The timings are also valid for inputs sampled on the negative clock edge. 1.5V FB_CLK(75MHz) TSETUP THOLD Input Setup And Hold Invalid 1.5V Valid 1.5V Invalid trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time FB_CLK Vh = VIH Vl = VIL FB4 FB5 Inputs Figure 13. General Input Timing Requirements 5.7.
Electrical Characteristics 5.7.1.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock. Table 11. FlexBus AC Timing Specifications Num Characteristic Symbol Min Frequency of Operation FB1 Clock Period (FB_CLK) FB2 Max Unit Notes 83.33 Mhz fsys/2 ns tcyc tFBCK 12 Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) tFBCHDCV — 7.
Electrical Characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB2 FB_D[31:X] FB5 ADDR[31:X] DATA FB4 FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB6 FB7 FB_TA Figure 14. FlexBus Read Timing S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB2 FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB6 FB7 FB_TA Figure 15. Flexbus Write Timing 5.8 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master.
Electrical Characteristics 5.8.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The SDRAM controller is a DDR controller with an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read.
Electrical Characteristics SD2 SD1 SD_CLK SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE CMD SD4 A[23:0] SD_BA[1:0] ROW COL SD11 SDDM SD12 WD1 D[31:0] WD2 WD3 WD4 Figure 16.
Electrical Characteristics 5.8.2 DDR SDRAM AC Timing Characteristics When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early board design. Please contact your local Freescale representative if questions develop. Table 13.
Electrical Characteristics 7 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 8 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid.
Electrical Characteristics DD1 DD2 SD_CLK DD3 SD_CLK CL=2 DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS CMD CL=2.5 DD4 A[13:0] ROW COL DD9 DQS Read Preamble CL = 2 SD_DQS3/SD_DQS2 DQS Read Postamble DD10 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble CL = 2.5 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 Figure 19. DDR Read Timing 5.9 General Purpose I/O Timing Table 14.
Electrical Characteristics FB_CLK G2 G1 GPIO Outputs G3 G4 GPIO Inputs Figure 20. GPIO Timing 5.10 Reset and Configuration Override Timing Table 15. Reset and Configuration Override Timing Num Characteristic Symbol Min Max Unit R1 RESET Input valid to FB_CLK High tRVCH 9 — ns R2 FB_CLK High to RESET Input invalid tCHRI 1.5 — ns R3 RESET Input valid Time 1 tRIVT 5 — tCYC R4 FB_CLK High to RSTOUT Valid tCHROV — 10 ns R5 RSTOUT valid to Config.
Electrical Characteristics NOTE Refer to the MCF5208 Reference Manual for more information. 5.11 I2C Input/Output Timing Specifications Table 16 and Table 17 list specifications for the I2C input and output timing parameters. Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Unit I1 Start condition hold time 2 — tcyc I2 Clock low period 8 — tcyc I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.
Electrical Characteristics I2 I6 I5 I2C_SCL I1 I4 I3 I8 I9 I7 I2C_SDA Figure 22. I2C Input/Output Timings 5.12 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V. 5.12.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK) The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement.
Electrical Characteristics 5.12.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK) Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. In addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency. Table 19.
Electrical Characteristics 5.12.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 21.
Electrical Characteristics 5.13 32-Bit Timer Module AC Timing Specifications Table 22 lists timer module AC timings. Table 22. Timer Module AC Timing Specifications Name Characteristic Unit Min Max T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — tCYC T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — tCYC 5.14 QSPI Electrical Specifications Table 23 lists QSPI timings. Table 23.
Electrical Characteristics 5.15 JTAG and Boundary Scan Timing Table 24.
Electrical Characteristics TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 29. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 30. Test Access Port Timing TCLK J14 TRST J13 Figure 31. TRST Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
Electrical Characteristics 5.16 Debug AC Timing Specifications Table 25 lists specifications for the debug AC timing parameters shown in Figure 32. Table 25. Debug AC Timing Specification Num Characteristic Min Max Unit D0 PSTCLK cycle time 1 1 tSYS D1 PSTCLK rising to PSTDDATA valid — 3.0 ns D2 PSTCLK rising to PSTDDATA invalid 1.
Revision History 6 Revision History Table 26. Revision History Revision Number Date 0 5/23/2005 • Initial Release 0.1 6/16/2005 • Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed FEC functionality, which are actually UART 0/1 clear-to-send and request-to-send signals. • Changed maximum core frequency in Table 10, spec #2, from 240MHz to 166.67MHz. Also, changed symbols in table: fcore -> fsys and fsys -> fsys/2 for consistency throughout document and reference manual. 0.
Revision History Table 26. Revision History (continued) Revision Number Date Substantive Changes 0.4 10/10/2005 • Figure 1 and Table 3: Changed pin 33 from EVDD to SD_VDD • Figure 4 and Table 3: Changed ball D10 from TEST to VSS • Figure 6 and Table 3: Changed pin 39 from EVDD to SD_VDD and pin 117 from TEST to VSS 0.5 3/29/2006 • Added “top view” and “bottom view” labels where appropriate to mechanical drawings and pinouts.
Revision History MCF5208 ColdFire® Microprocessor Data Sheet, Rev.
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