Datasheet

Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1)
MC9S12E256 Data Sheet, Rev. 1.10
98 Freescale Semiconductor
2.3.2.8 Flash Command Register (FCMD)
The banked FCMD register is the Flash command register.
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
2.3.2.9 Flash Control Register (FCTL)
The banked FCTL register is the Flash control register.
All bits in the FCTL register are readable but are not writable.
The FCTL register is loaded from the Flash Configuration Field byte at $FF0E during the reset sequence,
indicated by F in Figure 2-13.
Module Base + 0x0006
76543210
R0
CMDB
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-12. Flash Command Register (FCMD - NVM User Mode)
Table 2-18. FCMD Field Descriptions
Field Description
6-0
CMDB[6:0]
Flash Command — Valid Flash commands are shown in Table 2-19. Writing any command other than those
listed in Table 2-19 sets the ACCERR flag in the FSTAT register.
Table 2-19. Valid Flash Command List
CMDB[6:0] NVM Command
0x05 Erase Verify
0x06 Data Compress
0x20 Word Program
0x40 Sector Erase
0x41 Mass Erase
0x47 Sector Erase Abort
Module Base + 0x0007
76543210
R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
Reset F F FFFFFF
= Unimplemented or Reserved
Figure 2-13. Flash Control Register (FCTL)