Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 437
13.3.3.16 Pulse Accumulator Flag Register (PAFLG)
Read or write anytime.
Table 13-18. Pin Action
PAMOD PEDGE Pin Action
0 0 Falling edge
0 1 Rising edge
1 0 Divide by 64 clock enabled with pin high level
1 1 Divide by 64 clock enabled with pin low level
Table 13-19. Timer Clock Selection
CLK1 CLK0 Timer Clock
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
1 1 Use PACLK/65536 as timer counter clock frequency
Module Base + 0x0021
76543210
R000000
PAOVF PAIF
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-18. Pulse Accumulator Flag Register (PAFLG)
Table 13-20. PAFLG Field Descriptions
Field Description
1
PAOVF
Pulse Accumulator Overflow Flag — Writing a one to this bit clears it, writing a zero has not effect.
0 Flag indicates that there is no overflow condition of pulse accumulator counter.
1 Flag indicates overflow condition of pulse accumulator counter from $FFFF to $0000.
0
PAIF
Pulse Accumulator Input Edge Flag — In event mode the event edge triggers PAIF and in gated time
accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF. Writing a one to this
bit clears it, writing a zero has not effect. Any access to the PACNT register will clear all the flags in this register
when TFFCA bit of TSCR register is set.
0 Flag indicates that no selected edge has been detected on the IOC7 input pin.
1 Flag indicates that the selected edge is detected on the IOC7 input pin.