Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
368 Freescale Semiconductor
NOTE
IPOLx bits are buffered so only one PWM register is used per PWM cycle.
If an IPOLx bit changes during a PWM period, the new value does not take
effect until the next PWM period.
IPOLx bits take effect at the end of each PWM cycle regardless of the state
of the load okay bit, LDOK.
Figure 11-54. Internal Correction Logic when ISENS = 01
To detect the current status, the voltage on each ISx pin is sampled twice in a PWM period, at the end of
each deadtime. The value is stored in the DTx bits in the PMF Deadtime Sample register (PMFDTMS).
The DTx bits are a timing marker especially indicating when to toggle between PWM value registers.
Software can then set the IPOLx bit to toggle PMFVAL registers according to DTx values.
Table 11-39. Top/Bottom Manual Correction
Bit Logic state Output Control
IPOLA 0 PMFVAL0 controls PWM0/PWM1 pair
1 PMFVAL1 controls PWM0/PWM1 pair
IPOLB 0 PMFVAL2 controls PWM2/PWM3 pair
1 PMFVAL3 controls PWM2/PWM3 pair
IPOLC 0 PMFVAL4 controls PWM4/PWM5 pair
1 PMFVAL5 controls PWM4/PWM5 pair
DEADTIME
GENERATOR
DQ
CLK
IPOLx BIT
A/B
A
B
TOP PWM
BOTTOM PWM
PWM CYCLE START
PWM CONTROLLED
BY ODD PWMVAL REGISTER
PWM CONTROLLED
BY EVEN PWMVAL REGISTER