Datasheet

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 73
NOTE
All VSS pins must be connected together in the application. Because fast
signal transitions place high, short-duration current demands on the power
supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on
MCU pin load.
Table 1-5. MC9S12E128 Power and Ground Connection Summary
Mnemonic
Nominal
Voltage
Description
VDD1, VDD2 2.5 V Internal power and ground generated by internal regulator. These also allow an external
source to supply the core VDD/VSS voltages and bypass the internal voltage regulator.
VSS1, VSS2 0V
VDDR 3.3/5.0 V External power and ground, supply to internal voltage regulator.
To disable voltage regulator attach V
DDR
to V
SSR
.
VSSR 0 V
VDDX 3.3/5.0 V External power and ground, supply to pin drivers.
VSSX 0 V
VDDA 3.3/5.0 V Operating voltage and ground for the analog-to-digital converter, the reference for the
internal voltage regulator and the digital-to-analog converters, allows the supply voltage to
the A/D to be bypassed independently.
VSSA 0 V
VRH 3.3/5.0 V Reference voltage high for the ATD converter, and DAC.
VRL 0 V Reference voltage low for the ATD converter.
VDDPLL 2.5 V Provides operating voltage and ground for the Phased-Locked Loop. This allows the
supply voltage to the PLL to be bypassed independently. Internal power and ground
generated by internal regulator.
VSSPLL 0 V