Datasheet

Chapter 6 Analog-to-Digital Converter (ATD10B16CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 213
6.3.2.4 ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze
Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
76543210
R0
S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
Reset 0 0 1 00000
= Unimplemented or Reserved
Figure 6-6. ATD Control Register 3 (ATDCTL3)
Table 6-4. ATDCTL3 Field Descriptions
Field Description
6
S8C
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 6-5 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
5
S4C
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 6-5 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
4
S2C
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 6-5 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
3
S1C
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 6-5 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.