Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
128 Freescale Semiconductor
3.3.1 Port AD
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU)
interrupts. Each pin is assigned to these modules according to the following priority: ATD > KWU >
general-purpose I/O.
For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN0 and ATDDIEN1
registers in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN0 and
ATDDIEN1 registers do not affect the port AD pins when they are configured as outputs.
0x0020 Port Q I/O Register (PTQ) R/W
0x0021 Port Q Input Register (PTIQ) R
0x0022 Port Q Data Direction Register (DDRQ) R/W
0x0023 Port Q Reduced Drive Register (RDRQ) R/W
0x0024 Port Q Pull Device Enable Register (PERQ) R/W
0x0025 Port Q Polarity Select Register (PPSQ) R/W
0x0026 - 0x0027 Reserved —
0x0028 Port U I/O Register (PTU) R/W
0x0029 Port U Input Register (PTIU) R
0x002A Port U Data Direction Register (DDRU) R/W
0x002B Port U Reduced Drive Register (RDRU) R/W
0x002C Port U Pull Device Enable Register (PERU) R/W
0x002D Port U Polarity Select Register (PPSU) R/W
0x002E Port U Module Routing Register (MODRR) R/W
0x002F Reserved —
0x0030 Port AD I/O Register (PTAD) R/W
0x0031
0x0032 Port AD Input Register (PTIAD) R
0x0033
0x0034 Port AD Data Direction Register (DDRAD) R/W
0x0035
0x0036 Port AD Reduced Drive Register (RDRAD) R/W
0x0037
0x0038 Port AD Pull Device Enable Register (PERAD) R/W
0x0039
0x003A Port AD Polarity Select Register (PPSAD) R/W
0x003B
0x003D Port AD Interrupt Enable Register (PIEAD) R/W
0x003D
0x003E Port AD Interrupt Flag Register (PIFAD) R/W
0x003F
Table 3-2. PIM9HZ256 Memory Map (continued)
Address Offset Use Access