Datasheet
Chapter 2 Port Integration Module (PIM9C32) Block Description
96 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
2.3.2.4.7 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Write: Anytime.
2.3.2.4.8 Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
Module Base + 0x001E
76543210
R
PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
Reset 0 0 0 00000
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Table 2-26. PIEP Field Descriptions
Field Description
7–0
PIEP[7:0]
Pull Select Port P — This register disables or enables on a per pin basis the edge sensitive external interrupt
associated with port P.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Module Base + 0x001F
76543210
R
PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
Reset 0 0 0 00000
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Table 2-27. PIFP Field Descriptions
Field Description
7–0
PIFP[7:0]
Interrupt Flags Port P — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSP register. To clear this flag, write a “1” to the corresponding bit
in the PIFP register. Writing a “0” has no effect.
0 No active edge pending.
Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.