Datasheet

Chapter 2 Port Integration Module (PIM9C32) Block Description
94 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
2.3.2.4.3 Port P Data Direction Register (DDRP)
Read: Anytime.
Write: Anytime.
2.3.2.4.4 Port P Reduced Drive Register (RDRP)
Read: Anytime.
Write: Anytime.
Module Base + 0x001A
76543210
R
DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
Reset 0 0 0 00000
Figure 2-26. Port P Data Direction Register (DDRP)
Table 2-22. DDRP Field Descriptions
Field Description
7–0
DDRP[7:0]
Data Direction Port P — This register configures each port P pin as either input or output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP
or PTIP registers, when changing the DDRP register.
Module Base + 0x001B
76543210
R
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
W
Reset 0 0 0 00000
Figure 2-27. Port P Reduced Drive Register (RDRP)
Table 2-23. RDRP Field Descriptions
Field Description
7–0
RDRP[7:0]
Reduced Drive Port P — This register configures the drive strength of each port P output pin as either full or
reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.