Datasheet

Chapter 2 Port Integration Module (PIM9C32) Block Description
82 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
2.3.2.1.2 Port T Input Register (PTIT)
Read: Anytime.
Write: Never, writes to this register have no effect.
2.3.2.1.3 Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
Module Base + 0x0001
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset — — ——————
= Unimplemented or Reserved
Figure 2-4. Port T Input Register (PTIT)
Table 2-4. PTIT Field Descriptions
Field Description
7–0
PTIT[7:0]
Port T Input Register — This register always reads back the status of the associated pins. This can also be
used to detect overload or short circuit conditions on output pins.
Module Base + 0x0002
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 0 0 0 00000
Figure 2-5. Port T Data Direction Register (DDRT)
Table 2-5. DDRT Field Descriptions
Field Description
7–0
DDRT[7:0]
Data Direction Port T — This register configures each port T pin as either input or output.
The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM module port
associated with an enabled output compare. In these cases the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer input capture always monitors the state of the pin.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT
or PTIT registers, when changing the DDRT register.