Datasheet

Chapter 2 Port Integration Module (PIM9C32) Block Description
74 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
2.1.2 Block Diagram
Figure 2-1 is a block diagram of the PIM.
Figure 2-1. PIM Block Diagram
Note: The MODRR register within the PIM allows for mapping of PWM channels to Port T in the absence
of Port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use
MODRR since this is intended to support PWM channel availability in low pin count packages. Note that
Port T
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
TIM
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
Port P
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
Port S
PS0
PS1
PM2
PM3
PM4
PM5
PM0
PM1
RXD
TXD
RXCAN
TXCAN
MISO
MOSI
SCK
SS
SCI
CAN
SPI
Port J
PJ7
Port Integration Module
IRQ Logic
Interrupt Logic
Port B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port E
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
ADDR8/DATA8
ADDR9/DATA9
ADDR10/DATA10
ADDR11/DATA11
ADDR12/DATA12
ADDR13/DATA13
ADDR14/DATA14
ADDR15/DATA15
ADDR0/DATA0
ADDR1/DATA1
ADDR2/DATA2
ADDR3/DATA3
ADDR4/DATA4
ADDR5/DATA5
ADDR6/DATA6
ADDR7/DATA7
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
IPIPE0/MODA
NOACC/
XCLKS
IPIPE1/MODB
CORE
BKGD/MODC/TAGHI
BKGD
PJ6
Port M
A/D
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
ATD
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PS2
PS3
PWM
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
MUX