Datasheet

Appendix A Electrical Characteristics
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 675
Rev 01.24
In Table A-21 the timing characteristics for master mode are listed.
A.6.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
Figure A-8. SPI Slave Timing (CPHA=0)
Table A-21. SPI Master Mode Timing Characteristics
Num C Characteristic Symbol Min Typ Max Unit
1 P SCK Frequency f
sck
1/2048 — 1/2f
bus
1 P SCK Period t
sck
2 — 2048 t
bus
2 D Enable Lead Time t
lead
— 1/2 — t
sck
3 D Enable Lag Time t
lag
— 1/2 — t
sck
4 D Clock (SCK) High or Low Time t
wsck
— 1/2 — t
sck
5 D Data Setup Time (Inputs) t
su
8——ns
6 D Data Hold Time (Inputs) t
hi
8——ns
9 D Data Valid after SCK Edge t
vsck
— — 30 ns
10 D Data Valid after
SS fall (CPHA=0) t
vss
— — 15 ns
11 D Data Hold Time (Outputs) t
ho
20 — — ns
12 D Rise and Fall Time Inputs t
rfi
—— 8 ns
13 D Rise and Fall Time Outputs t
rfo
—— 8 ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
1
9
5 6
MSB IN
BIT 6 . . . 1
LSB IN
SLAVE MSB
SLAVE LSB OUT
BIT 6 . . . 1
11
4
4
2
7
(CPOL = 0)
(CPOL = 1)
3
13
NOTE: Not defined!
12
12
11
SEE
13
NOTE
8
10
see
note