Datasheet

Appendix A Electrical Characteristics
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 667
Rev 01.24
The loop bandwidth f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
C
=10kHz:
The capacitance C
s
can now be calculated as:
The capacitance C
p
should be chosen in the range of:
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f
cmp
, the
deviation from the reference clock f
ref
is measured and input voltage to the VCO is adjusted accordingly.
The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage,
temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter
affects the real minimum and maximum clock periods as illustrated in Figure A-4.
f
C
2 ζ f
ref
⋅⋅
πζ 1 ζ
2
++
⎝⎠
⎛⎞
⋅
------------------------------------------
1
10
-----
f
C
f
ref
410⋅
------------- ζ 0.9=();<→⋅<
f
C
< 25kHz
n
f
VCO
f
ref
------------- 2 s y n r 1+()⋅==
= 50
R
2 π nf
C
⋅⋅⋅
K
Φ
-----------------------------=
=2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
C
s
2 ζ
2
⋅
π f
C
R⋅⋅
----------------------
0.516
f
C
R⋅
--------------- ζ 0.9=();≈=
= 5.19nF =~ 4.7nF
C
s
20⁄ C
p
C
s
10⁄≤≤
C
p
= 470pF