Datasheet

Appendix A Electrical Characteristics
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 663
Rev 01.24
A.3 MSCAN
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-15 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
A.4.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.4.1.2 LVR
The release level V
LVRR
and the assert level V
LVRA
are derived from the V
DD
supply. They are also valid
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
Table A-14. MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P MSCAN Wake-up dominant pulse filtered t
WUP
—— 2 us
2 P MSCAN Wake-up dominant pulse pass t
WUP
5—us
Table A-15. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 T POR release level V
PORR
2.07 V
2 T POR assert level V
PORA
0.97 V
3 D Reset input pulse width, minimum input time PW
RSTL
2—t
osc
4 D Startup from Reset n
RST
192 196 n
osc
5D
Interrupt pulse width,
IRQ edge-sensitive
mode
PW
IRQ
20 ns
6 D Wait recovery startup time t
WRS
14 t
cyc