Datasheet

Appendix A Electrical Characteristics
658 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
V
RL
is not available as a separate pin in the 48- and 52-pin versions. In this case the internal V
RL
pad is
bonded to the V
SSA
pin.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD
accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
A.2.1 ATD Operating Characteristics In 5V Range
The Table A-10 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results: V
SSA
≤ V
RL
≤ V
IN
≤ V
RH
≤ V
DDA
.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-10. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= V
DDA
<=5V+10%
Num C Rating Symbol Min Typ Max Unit
1D
Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA/2
—
—
V
DDA/2
V
DDA
V
V
2 C Differential Reference Voltage
(1)
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
V
RH
-V
RL
4.75 5.0 5.25 V
3 D ATD Clock Frequency f
ATDCLK
0.5 — 2.0 MHz
4D
ATD 10-Bit Conversion Period
Clock Cycles
(2)
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
N
CONV10
T
CONV10
14
7
—
—
28
14
Cycles
µs
5D
ATD 8-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV10
T
CONV10
12
6
—
—
26
13
Cycles
µs
5 D Recovery Time (V
DDA
=5.0 Volts) t
REC
——20µs
6 P Reference Supply current I
REF
— — 0.375 mA