Datasheet

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 65
Rev 01.24
1.8 Recommended Printed Circuit Board Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins.
• Central point of the ground star should be the V
SSR
pin.
• Use low ohmic low inductance connections between V
SS1
, V
SS2
, and V
SSR
.
•V
SSPLL
must be directly connected to V
SSR
.
• Keep traces of V
SSPLL
, EXTAL, and XTAL as short as possible and occupied board area for C6,
C7, C11, and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C6, C7, C5, and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the V
DDA
/V
SSA
pins.
Table 1-12. Recommended Component Values
Component Purpose Type Value
C1 V
DD1
filter capacitor Ceramic X7R 220nF, 470nF
(1)
1. In 48LQFP and 52LQFP package versions, V
DD2
is not available. Thus 470nF must be connected to
V
DD1
.
C2 V
DDR
filter capacitor X7R/tantalum >=100nF
C3 V
DDPLL
filter capacitor Ceramic X7R 100nF
C4 PLL loop filter capacitor
See PLL specification chapter
C5 PLL loop filter capacitor
C6 OSC load capacitor
See PLL specification chapter
C7 OSC load capacitor
C8 V
DD2
filter capacitor (80 QFP only) Ceramic X7R 220nF
C9 V
DDA
filter capacitor Ceramic X7R 100nF
C10 V
DDX
filter capacitor X7R/tantalum >=100nF
C11 DC cutoff capacitor
Colpitts mode only, if recommended by
quartz manufacturer
R1 Pierce Mode Select Pullup Pierce Mode Only
R2 PLL loop filter resistor See PLL Specification chapter
R3 / R
B
PLL loop filter resistor
Pierce mode only
R4 / R
S
PLL loop filter resistor
Q1 Quartz — —