Datasheet

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 61
Rev 01.24
0xFFDE, 0xFFDF Standard timer overflow I bit TMSK2 (TOI) 0x00DE
0xFFDC, 0xFFDD Pulse accumulator A overflow I bit PACTL (PAOVI) 0x00DC
0xFFDA, 0xFFDB Pulse accumulator input edge I bit PACTL (PAI) 0x00DA
0xFFD8, 0xFFD9 SPI I bit SPICR1 (SPIE, SPTIE) 0x00D8
0xFFD6, 0xFFD7 SCI I bit
SCICR2
(TIE, TCIE, RIE, ILIE)
0x00D6
0xFFD4, 0xFFD5
Reserved
0xFFD2, 0xFFD3 ATD I bit ATDCTL2 (ASCIE) 0x00D2
0xFFD0, 0xFFD1
Reserved
0xFFCE, 0xFFCF Port J I bit PIEP (PIEP7-6) 0x00CE
0xFFCC, 0xFFCD
Reserved
0xFFCA, 0xFFCB
Reserved
0xFFC8, 0xFFC9
Reserved
0xFFC6, 0xFFC7 CRG PLL lock I bit PLLCR (LOCKIE) 0x00C6
0xFFC4, 0xFFC5 CRG self clock mode I bit PLLCR (SCMIE) 0x00C4
0xFFBA to 0xFFC3
Reserved
0xFFB8, 0xFFB9 FLASH I bit FCNFG (CCIE, CBEIE) 0x00B8
0xFFB6, 0xFFB7
CAN wake-up
(1)
I bit CANRIER (WUPIE) 0x00B6
0xFFB4, 0xFFB5
CAN errors
1
I bit CANRIER (CSCIE, OVRIE) 0x00B4
0xFFB2, 0xFFB3
CAN receive
1
I bit CANRIER (RXFIE) 0x00B2
0xFFB0, 0xFFB1
CAN transmit
1
I bit CANTIER (TXEIE[2:0]) 0x00B0
0xFF90 to 0xFFAF
Reserved
0xFF8E, 0xFF8F Port P I bit PIEP (PIEP7-0) 0x008E
0xFF8C, 0xFF8D
Reserved
0xFF8C, 0xFF8D PWM Emergency Shutdown I bit PWMSDN(PWMIE) 0x008C
0xFF8A, 0xFF8B VREG LVI I bit CTRL0 (LVIE) 0x008A
0xFF80 to 0xFF89
Reserved
1. Not available on MC9S12GC Family members
Table 1-9. Interrupt Vector Locations (continued)
Vector Address Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate