Datasheet

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)

60 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor

Rev 01.24

1.5.3.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay

active. For further power consumption reduction the peripherals can individually turn off their local clocks.

1.5.3.4 Run

Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save

power.

1.6 Resets and Interrupts

Consult the Exception Processing section of the CPU12 Reference Manual for information.

1.6.1 Vectors

Table 1-9 lists interrupt sources and vectors in default order of priority.

Table 1-9. Interrupt Vector Locations

Vector Address Interrupt Source

CCR

Mask

Local Enable

HPRIO Value

to Elevate

0xFFFE, 0xFFFF

External reset, power on reset,

or low voltage reset

(see CRG ﬂags register to determine

reset source)

None None —

0xFFFC, 0xFFFD Clock monitor fail reset None COPCTL (CME, FCME) —

0xFFFA, 0xFFFB COP failure reset None COP rate select —

0xFFF8, 0xFFF9 Unimplemented instruction trap None None —

0xFFF6, 0xFFF7 SWI None None —

0xFFF4, 0xFFF5 XIRQ X-Bit None —

0xFFF2, 0xFFF3 IRQ I bit INTCR (IRQEN) 0x00F2

0xFFF0, 0xFFF1 Real time Interrupt I bit CRGINT (RTIE) 0x00F0

0xFFEE, 0xFFEF Standard timer channel 0 I bit TIE (C0I) 0x00EE

0xFFEC, 0xFFED Standard timer channel 1 I bit TIE (C1I) 0x00EC

$FFEE, $FFEF

Reserved

$FFEC, $FFED

Reserved

0xFFEA, 0xFFEB Standard timer channel 2 I bit TIE (C2I) 0x00EA

0xFFE8, 0xFFE9 Standard timer channel 3 I bit TIE (C3I) 0x00E8

0xFFE6, 0xFFE7 Standard timer channel 4 I bit TIE (C4I) 0x00E6

0xFFE4, 0xFFE5 Standard timer channel 5 I bit TIE (C5I) 0x00E4

0xFFE2, 0xFFE3 Standard timer channel 6 I bit TIE (C6I) 0x00E2

0xFFE0, 0xFFE1 Standard timer channel 7 I bit TIE (C7I) 0x00E0