Datasheet

Chapter 18 32 Kbyte Flash Module (S12FTS32KV1)
522 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
Figure 18-21. PRDIV8 and FDIV Bits Determination Procedure
PRDIV8=1
yes
no
PRDIV8=0 (reset)
12.8MHz?
FCLK=(PRDCLK)/(1+FDIV[5:0])
PRDCLK=oscillator_clock
PRDCLK=oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[ms])
no
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ms])-1
yes
START
Tbus < 1ms?
an integer?
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ms]))
1/FCLK[MHz] + Tbus[ms] > 5
AND
FCLK > 0.15MHz
?
END
yes
no
FDIV[5:0] > 4?
ALL COMMANDS IMPOSSIBLE
yes
no
ALL COMMANDS IMPOSSIBLE
no
TRY TO DECREASE Tbus
yes
oscillator_clock