Datasheet
Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
48 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
1.3.2 Signal Properties Summary
Table 1-5. Signal Properties
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Power
Domain
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL — — V
DDPLL
NA NA Oscillator pins
XTAL — — V
DDPLL
NA NA
RESET — — V
DDX
None None External reset pin
XFC — — V
DDPLL
NA NA PLL loop filter pin
TEST V
PP
— V
SSX
NA NA Test pin only
BKGD MODC
TAGHI V
DDX
Up Up Background debug, mode pin, tag signal high
PE7 NOACC
XCLKS V
DDX
PUCR Up Port E I/O pin, access, clock select
PE6 IPIPE1 MODB V
DDX
While RESET
pin is low: Down
Port E I/O pin and pipe status
PE5 IPIPE0 MODA V
DDX
While RESET
pin is low: Down
Port E I/O pin and pipe status
PE4 ECLK — V
DDX
PUCR
Mode
Dep
(1)
Port E I/O pin, bus clock output
PE3 LSTRB
TAGLO V
DDX
PUCR
Mode
Dep
1
Port E I/O pin, low strobe, tag signal low
PE2 R/
W—V
DDX
PUCR
Mode
Dep
1
Port E I/O pin, R/W in expanded modes
PE1
IRQ — V
DDX
PUCR Up Port E input, external interrupt pin
PE0
XIRQ — V
DDX
PUCR Up Port E input, non-maskable interrupt pin
PA[7:3]
ADDR[15:1/
DATA[15:1]
—V
DDX
PUCR Disabled
Port A I/O pin and multiplexed address/data
PA[2:1]
ADDR[10:9/
DATA[10:9]
—V
DDX
PUCR Disabled
Port A I/O pin and multiplexed address/data
PA[0]
ADDR[8]/
DATA[8]
—V
DDX
PUCR Disabled
Port A I/O pin and multiplexed address/data
PB[7:5]
ADDR[7:5]/
DATA[7:5]
—V
DDX
PUCR Disabled
Port B I/O pin and multiplexed address/data
PB[4]
ADDR[4]/
DATA[4]
—V
DDX
PUCR Disabled
Port B I/O pin and multiplexed address/data
PB[3:0]
ADDR[3:0]/
DATA[3:0]
—V
DDX
PUCR Disabled
Port B I/O pin and multiplexed address/data
PAD[7:0] AN[7:0] — V
DDA
PERAD/P
PSAD
Disabled
Port AD I/O pins and ATD inputs
PP[7] KWP[7] — V
DDX
PERP/
PPSP
Disabled
Port P I/O pins and keypad wake-up
PP[6] KWP[6] ROMCTL V
DDX
PERP/
PPSP
Disabled
Port P I/O pins, keypad wake-up, and ROMON
enable.
PP[5] KWP[5] PW5 V
DDX
PERP/
PPSP
Disabled
Port P I/O pin, keypad wake-up, PW5 output
PP[4:3] KWP[4:3] PW[4:3] V
DDX
PERP/
PPSP
Disabled
Port P I/O pin, keypad wake-up, PWM output