Datasheet

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 457
Rev 01.24
15.3.2.17 Pulse Accumulators Count Registers (PACNT)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an active
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
15.4 Functional Description
This section provides a complete functional description of the timer TIM16B8CV1 block. Please refer to
the detailed timer block diagram in Figure 15-28 as necessary.
Module Base + 0x0022
15 14 13 12 11 10 9 0
R
PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8
W
Reset 0 0 0 00000
Figure 15-26. Pulse Accumulator Count Register High (PACNTH)
Module Base + 0x0023
76543210
R
PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0
W
Reset 0 0 0 00000
Figure 15-27. Pulse Accumulator Count Register Low (PACNTL)