Datasheet

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 451
Rev 01.24
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
15.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Table 15-15. TSCR2 Field Descriptions
Field Description
7
TOI
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
3
TCRE
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for
a more detail explanation please refer to Section 15.4.3, “Output Compare
2
PR[2:0]
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 15-16.
Table 15-16. Timer Clock Selection
PR2 PR1 PR0 Timer Clock
0 0 0 Bus Clock / 1
0 0 1 Bus Clock / 2
0 1 0 Bus Clock / 4
0 1 1 Bus Clock / 8
1 0 0 Bus Clock / 16
1 0 1 Bus Clock / 32
1 1 0 Bus Clock / 64
1 1 1 Bus Clock / 128
Module Base + 0x000E
76543210
R
C7F C6F C5F C4F C3F C2F C1F C0F
W
Reset 0 0 0 00000
Figure 15-20. Main Timer Interrupt Flag 1 (TFLG1)