Datasheet

Chapter 15 Timer Module (TIM16B8CV1) Block Description
450 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
15.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
15.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Module Base + 0x000C
76543210
R
C7I C6I C5I C4I C3I C2I C1I C0I
W
Reset 0 0 0 00000
Figure 15-18. Timer Interrupt Enable Register (TIE)
Table 15-14. TIE Field Descriptions
Field Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
Module Base + 0x000D
76543210
R
TOI
000
TCRE PR2 PR1 PR0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 15-19. Timer System Control Register 2 (TSCR2)